JPH02101539A - System for detecting runaway of cpu - Google Patents

Abstract

PURPOSE:To accurately judge the cause of the reset of CPU by providing power failure detection FF which is made into a a set state by means of CPU and reset by means of power failure detection signal from a power failure detection circuit. CONSTITUTION:When a power unit is turned on, JK-FF 24 is made to the set state by CPU 2. When power failure occurs and the power failure detection signal S1 is inputted to CPU 2 from the power failure detection circuit 18 with a reset signal, FF 24 is made to the reset state by simultaneously inputting the signal S1 to FF 24. CPU 24 judges whether the inputted reset signal is the signal S1 or a time up signal S3 from the output state of an output terminal Q in FF 24. When CPU 2 has a run away and the signal S3 is inputted to CPU 2 as the reset signal on the other hand, CPU 2 reads the output state of FF 24, and judges it to be the runaway of CPU 2. Consequently, it can accurately be judged that the reset of CPU 2 is due to the power failure or the runaway.

Description

[Detailed description of the invention] (Field of invention) The present invention relates to a CPU runaway detection method.

(Prior art and its problems) FIG. 3 is an overall circuit diagram including a CPU, a conventional circuit for detecting runaway of the CPU, and other circuits. In FIG. 3, 2 is a CPU equipped with a reset terminal 2a, a data bus output terminal 2b, and an address bus output terminal 2c, 4 is an address decoder, 6 is an input circuit, and 8
10 is an output circuit, 10 is a ROM, 12 is a RAM, 14 is a data bus, and 16 is an address bus. Since these are well-known configurations in microcomputer technology, their explanation will be omitted.

18 is a power outage detection circuit that detects a power outage and outputs a power outage detection signal S1 at the time of detection; 20 is a circuit that can reset the timer operation in response to the input of a toggle signal S2 from the CPU 2 via the address decoder 4;
a watchdog timer circuit that continues its operation until the time-up time after the timer operates because the toggle signal S2 is no longer input due to runaway of U2, and outputs a time-up signal S3 when the time-up occurs;
22 converts the power failure detection signal Sl and time-up signal S3 to C.
This is an OR circuit that outputs to the reset terminal 2a of PU2.

In the circuit having the above configuration, first, when the CPU 2 is in normal operation, the CPU 2 sends the watchdog timer circuit 20 to the watchdog timer circuit 20.
Toggle signal S2 with a cycle shorter than the time-up time of 0
By outputting, the watchdog timer circuit 2
0 does not time up, so the watchdog timer circuit 20 does not output the time up signal S3. Further, when the power outage detection circuit 18 does not detect a power outage, the power outage detection circuit 18 outputs a power outage detection signal Sl.
is not output.

On the other hand, when the CPU 2 goes out of control and the toggle signal S2 is no longer input to the watchdog timer circuit 20, the watchdog timer circuit 20 times up and the watchdog timer circuit 20 outputs the toggle signal S2 to the CPU 2 via the OR circuit 22. Time-up signal S3 to reset terminal 2a
is input as a reset signal, so that the CPU 2 responds to the reset signal and resets the program execution operation to the initial state. Further, when a power outage state is detected by the power outage detection circuit 18, the power outage detection signal Sl from the power outage detection circuit 18 is inputted as a reset signal to the reset terminal 2a of the CPU 2 via the OR circuit 22.
Similarly, the program execution operation of PU2 is reset to the initial state in response to the reset signal.

Therefore, in the above configuration, the reset terminal 2 of the CPU 2
A has a power outage detection signal St from the power outage detection circuit 18 and a time-up signal S from the watchdog timer circuit 20.
3 and 3 are respectively input as reset signals to the CPU 2.
The program execution operation of the CPU 2 is started from the initial state, but the program processing of the CPU 2 is different depending on whether the reset signal is related to the power outage detection signal Sl or the time-up signal S3.
Second, it is necessary to accurately determine in which case the reset signal applies.

However, in the conventional example, both the power failure detection signal St and the time-up signal S3 are input as reset signals to the reset terminal 2a in the same form, so the CPU 2 cannot make accurate judgments, and the I was unable to respond.

(Object of the Invention) The present invention has been made in view of the above-mentioned circumstances. The purpose of this is to enable accurate judgment and to take appropriate measures in the event of a runaway program.

(Structure and Effects of the Invention) In order to achieve such an object, the present invention has the following features:
A power outage detection circuit that detects a power outage and outputs a power outage detection signal upon detection, and a timer operation that is reset in response to the input of a toggle signal, and that operates from the time the timer starts until the time-up time arrives. and a watchdog timer circuit that sometimes outputs a time-up signal, and the CPU in normal operation outputs a toggle signal to the watchdog timer circuit at a cycle shorter than the time-up time of the watchdog timer circuit, In a CPU runaway detection method configured to input a power failure detection signal from the power failure detection circuit and a time-up signal from the watchdog timer circuit as reset signals to a reset terminal of the CPU, the CPU The CPU includes a power outage detection flip-flop configured to be set to a first output state and set to a second output state upon input of a power outage detection signal from the power outage detection circuit; is configured to determine whether the reset signal applied to the reset terminal is the power failure detection signal or the time-up signal from the output state of the power failure detection flip-flop, while setting the power failure detection flip-flop to a first output state. It has the following characteristics.

According to the above configuration, the power failure detection circuit outputs the power failure detection signal at the time of power failure. When the CPU is operating normally, the watchdog timer circuit
When the CPU goes out of control, the watchdog timer circuit outputs a time-up signal when the time-up time arrives. When the power failure detection signal or time-up signal is applied as a reset signal to the reset terminal of the CPU, the CPU is reset.

In such a configuration, when the power failure detection flip-flop is set to the first output state, for example, the set state, by the CPU, the power failure detection signal from the power failure detection circuit is output to the CPU.
When a reset signal is input to the reset terminal of U, the power failure detection flip-flop is simultaneously put into a second output state, for example, a reset state by inputting the power failure detection signal, so that the CPU reset by the power failure detection signal
reads out that the power outage detection flip-flop is in the second output state, and can determine from the read content that it has been reset due to a power outage. Furthermore, when the power failure detection flip-flop is set, if the time-up signal from the watchdog timer circuit is input as a reset signal to the reset terminal of the CPU and the CPU is reset, the power failure detection flip-flop , the power failure detection flip-flop remains in the first output state. It is possible to read out that the CPU is in the output state, and to determine from the read contents that the reset has occurred due to CPU runaway.

Therefore, in the present invention, it is possible to accurately determine whether the CPU is reset due to a power failure or runaway by reading the output state of the power failure detection flip-flop.

(Description of Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram relating to a CPU runaway detection method according to an embodiment of the present invention, and the same symbols as those shown in FIG. 3 according to the conventional example are also used in this embodiment. Refers to parts or parts similar to those shown. Further, unless otherwise specified, the present embodiment and the conventional example have the same configuration with respect to connection relationships and the like.

The configuration of this embodiment differs from the conventional example as follows.

That is, in this embodiment, the C
The set signal inputted from PU2 is applied to the J terminal to set the set state (first output state), and the power failure detection signal S1 from the power failure detection circuit 18 is applied to the clear terminal CL.
is connected to the output terminal Q of the JK flip-flop 24 and the JK flip-flop 24 as a power failure detection flip-flop configured to be put into a reset state fiJ (second output state) by inputting to the CPU 2.
and a buffer 26 connected to the data bus 14 of.

Then, when executing the program, the CPU 2 sets the JK flip-flop 24 to a set state, that is, sets the potential level of its output terminal Q to "1", and sets the JK flip-flop 24 to "1".
4, it is determined whether the reset signal applied to the reset terminal 2a is the power failure detection signal Sl or the time-up signal S3.

The rest of the configuration is the same as the conventional example, so the explanation will be omitted.

Next, the operation of this embodiment will be explained according to the flowchart of FIG.

First, when the power is turned on and the program operation by the CPU 2 starts, the JK flip-flop 24 is activated by the CPU 2.
is set to the set state rlJ.

When a power outage occurs and the power outage detection signal St is input from the power outage detection circuit 18 to the reset terminal 2a of the CPU 2 as a reset signal, the power outage detection signal S1 is simultaneously input to the CL terminal of the JK flip-flop 24. The JK flip-flop 24 is in the reset state "0".
”. The CPU 2 determines whether the reset signal input to the reset terminal 2a is the power failure detection signal S1 or the time-up signal S3 from the output state of the output terminal Q of the JK flip-flop 24. In this case, since the output state of the output terminal Q is rOJ, it is determined as YES, and the reset signal input to the reset terminal 2a is determined to be related to the power outage detection signal Sl, and the corresponding program processing is performed. At the same time, the output state of the JK flip-flop 24 is set to the set state, and normal program processing is started.

On the other hand, the CPU2 goes out of control and the watchdog timer circuit 2
When the time-up signal S3 from 0 is input as a reset signal to its reset terminal 2a, the output state of the JK flip-flop 24 remains in the set state rlJ, but the CPU 2 reads the output state of the JK flip-flop 70 knob 24. If it is not "0", it is determined that the CPU 2 is running out of control, and corresponding processing is performed.

Therefore, in this embodiment, it is possible to accurately determine whether the reset of the CPU 2 is due to a power outage or a runaway by reading the output state of the JK flip-flop 24.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a CPU runaway detection method according to an embodiment of the present invention, and FIG. 2 is a flowchart for explaining the operation of the embodiment. FIG. 3 is a circuit diagram of a conventional CPU runaway detection method. 2...CPU11B...Power failure detection circuit, 20...
Watchdog timer circuit, 24...JK flip-flop (power failure detection flip-flop), St...power failure detection signal, S2...toggle signal, S3...time-up signal. Figure 1

Claims (1)

[Claims] (1) A power outage detection circuit that detects a power outage and outputs a power outage detection signal upon detection, and a power outage detection circuit that resets the timer operation in response to the input of a toggle signal, from the time the timer operation starts until the time up time arrives. and a watchdog timer circuit that outputs a time-up signal when the timer operates, and the CPU in normal operation toggles the watchdog timer circuit at a cycle shorter than the time-up time of the watchdog timer circuit. A runaway detection system for a CPU configured to output a signal and input a power failure detection signal from the power failure detection circuit and a time-up signal from the watchdog timer circuit as reset signals to a reset terminal of the CPU, respectively. A power outage detection flip-flop configured to be set to a first output state by the CPU and set to a second output state by input of a power outage detection signal from the power outage detection circuit, While setting the power failure detection flip-flop to a first output state during execution, it is determined from the output state of the power failure detection flip-flop whether the reset signal given to the reset terminal is the power failure detection signal or the time-up signal. A runaway detection method for a CPU configured to.