JPH02101539A - System for detecting runaway of cpu - Google Patents

System for detecting runaway of cpu

Info

Publication number
JPH02101539A
JPH02101539A JP63255569A JP25556988A JPH02101539A JP H02101539 A JPH02101539 A JP H02101539A JP 63255569 A JP63255569 A JP 63255569A JP 25556988 A JP25556988 A JP 25556988A JP H02101539 A JPH02101539 A JP H02101539A
Authority
JP
Japan
Prior art keywords
cpu
signal
power failure
reset
failure detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63255569A
Other languages
Japanese (ja)
Inventor
Yoichi Kitagawa
Original Assignee
Omron Tateisi Electron Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electron Co filed Critical Omron Tateisi Electron Co
Priority to JP63255569A priority Critical patent/JPH02101539A/en
Publication of JPH02101539A publication Critical patent/JPH02101539A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To accurately judge the cause of the reset of CPU by providing power failure detection FF which is made into a a set state by means of CPU and reset by means of power failure detection signal from a power failure detection circuit.
CONSTITUTION: When a power unit is turned on, JK-FF 24 is made to the set state by CPU 2. When power failure occurs and the power failure detection signal S1 is inputted to CPU 2 from the power failure detection circuit 18 with a reset signal, FF 24 is made to the reset state by simultaneously inputting the signal S1 to FF 24. CPU 24 judges whether the inputted reset signal is the signal S1 or a time up signal S3 from the output state of an output terminal Q in FF 24. When CPU 2 has a run away and the signal S3 is inputted to CPU 2 as the reset signal on the other hand, CPU 2 reads the output state of FF 24, and judges it to be the runaway of CPU 2. Consequently, it can accurately be judged that the reset of CPU 2 is due to the power failure or the runaway.
COPYRIGHT: (C)1990,JPO&Japio
JP63255569A 1988-10-11 1988-10-11 System for detecting runaway of cpu Pending JPH02101539A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63255569A JPH02101539A (en) 1988-10-11 1988-10-11 System for detecting runaway of cpu

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63255569A JPH02101539A (en) 1988-10-11 1988-10-11 System for detecting runaway of cpu

Publications (1)

Publication Number Publication Date
JPH02101539A true JPH02101539A (en) 1990-04-13

Family

ID=17280537

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63255569A Pending JPH02101539A (en) 1988-10-11 1988-10-11 System for detecting runaway of cpu

Country Status (1)

Country Link
JP (1) JPH02101539A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS596254B2 (en) * 1976-09-14 1984-02-09 Asahi Glass Co Ltd
JPS63191245A (en) * 1987-02-03 1988-08-08 Fujitsu Ltd Resetting control system for device being in runaway state

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS596254B2 (en) * 1976-09-14 1984-02-09 Asahi Glass Co Ltd
JPS63191245A (en) * 1987-02-03 1988-08-08 Fujitsu Ltd Resetting control system for device being in runaway state

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