JPS5855535B2 - Multi-computer device for vehicles - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reset device for a multi-computer device for a vehicle equipped with a plurality of computers.

In recent years, computers have come to be used to control engine systems, automatic transmissions, and calculate and display speeds and travel distances.As the types of loads that are controlled using computers increase, it has become easier to deal with this by installing multiple computer devices. There is a tendency to

In such a case, a multi-configuration that links mutual control between computers will be adopted, specifically a parent computer that monitors and controls the entire system, and a unique program control system under the supervision of this parent computer. This is a multi-configuration with a parent-child relationship, each with a computer that performs the following steps.

By the way, as a means of resetting a device with the above-mentioned multi-configuration, if we take the multi-configuration with two computers as shown in Fig. 1 as an example, as is clear from the time chart in Fig. 2, turning on the power switch 3 is necessary. When the power is turned on, a timer circuit 4 provided to avoid a reset in an unstable state immediately after the power is turned on generates an output that changes from the L level to the H level with a delay of a predetermined time td after the power is turned on.

In synchronization with this rise to H level from the timer circuit 4, the waveform shaping circuit 5 outputs the reset signal RESI, and inputs the reset signal RESI to the reset terminal 101 of the first computer device 1 (parent computer). , apply a reset.

Therefore, the initial setting program of the computer device 1 is executed, and the computer device 1 outputs a reset signal RES2 from the output terminal 102 to the reset terminal 201 of the second computer device 2 via the buffer circuit 6. It is configured to reset the .

By the way, as mentioned above, by turning on the power switch,
The reset method, which first resets the parent computer and then resets other computers using its initial setting program, has the advantage of simplifying the configuration of the reset circuit provided as an external circuit. It is possible to reliably perform a reset when the power is turned on without expanding the scale.

However, with the above reset method, after all computers are reset by turning on the power switch,
If one of the computers causes an arithmetic error, there is a problem in that program control continues with the arithmetic error occurring.

This application was made in view of the above, and in order to ensure the prevention of erroneous calculations, when any computer makes an erroneous calculation, it is determined by another computer and the computer that made the erroneous calculation is made to perform the calculation again. This is what I did.

Embodiments of the present invention will be described below based on the accompanying drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention.
．． Reference numeral 20 denotes a computer device, which has a multi-configuration that executes independent program control in parallel.

11 is a DC power supply, 12 is a power switch, 13 is a timer circuit, and 14 is a waveform shaping circuit. When the power switch 12 is turned on, a reset signal delayed by a predetermined time is sent to AND gates 15 and 16 in the same manner as in the conventional device. A reset signal RES1 is sent to the reset terminal of the computer 10゜20 through the
RES2 is applied.

That is, in the present invention, the reset at power-on directly resets all computers.

17° and 18 are inverters.

In the computers 10.20, 101 and 201 are output terminals for monitoring signals WAT1 and WAT2 that indicate whether the operation of each computer 10.20 is normal, and 102 and 202 are output terminals for monitoring signals from other computers. These are input terminals for inputting the signals WAT 2 and WAT 1, and further, 103 and 203 are output terminals for sending out a reset signal when an abnormal operation of another computer is detected.

The internal configuration of a computer that supports this input/output terminal is
FIG. 4 shows a computer 10 as an example.

In FIG. 4, 21 is an abnormality monitoring circuit that outputs a monitoring signal WATI to determine whether or not the operation of the computer 10 is normal. Specifically, it is a signal synchronized with the maximum machine cycle in which one program instruction is executed. In other words, a rectangular signal or the like representing the time width until the program counter changes to the next count is detected and output.

22 is an interface that receives the monitoring signal WAT2 from the computer 20, detects its rising or falling timing, and outputs it; 23 is the interface 22;
24 is a counter that counts the clocks applied while the gate signal is being applied from the timer circuit 23, and 25 is a count when the monitoring signal WAT2 indicates normal operation. The setter 26, which has set the number as a discrimination criterion, compares the counted value of the counter 24 with the reference value of the setter 24, and when the reference value is exceeded, it determines that the computer 20 has malfunctioned and outputs a reset signal RES. It is an abnormality detector.

Next, the operation in the above embodiment will be explained.

First, referring to FIG. 3, the operation when the power is turned on will be described.

The operation at this time is shown in the time chart of FIG.

That is, when the power switch 12 is turned on, power is applied to the computer 10.20, and when the power is turned on from OFF, when time td has elapsed, the output of the timer circuit 13 changes from L level to H level, and the waveform Shaping circuit 14
Then, reset pulses RES1 and RES2 (rise to H level) are applied to the computers 10.20 through the AND gates 15 and 16 to reset them, and each of the computers 10.20 executes predetermined program control in parallel. Start.

When this reset is applied, the inputs of inverters 17 and 18 are at L level, so the outputs of inverters 17 and 18 to AND gates 15 and 16 are at H level, and the output of waveform shaping circuit 14 rises from L level to H level. The rising reset condition is directly applied to the computer 10.20.

In this manner, when the computer 10.20 starts operating, the computer 10 mutually outputs the supervisory signal WAT1 to the computer 20, and the computer 20 mutually outputs the supervisory signal WAT2 to the computer 10.

Then, each of the computers 10.20 receives the sent supervisory signal WAT1. For example, the rise time width t1°t2. of WAT2. t3..., t1', t2', t3'
.
If it is within this range, it is assumed that normal operation is occurring, and the output terminals 103 and 203 are set to L level.

The details are shown in Figure 6, which shows the operation time chart in Figure 4.
This will become clear with reference to the figure.

That is, the interface 22 connects the computer 10
The rise time width t'1°t of the supervisory signal WAT2 input to
'2. t'3. ... sets the timer circuit 23,
Reset the time width t'1. t'2. t'3. ...
The timer output is applied to the counter 24 as a gate signal, and the gate width t'1. t'2. The clock is counted by the counter 24 every t'3... The abnormality detection circuit 26
When it is less than the reference value, the output of the abnormality determination circuit 26 becomes L level, and the computer 20 cannot be reset.

Now, suppose that the computer 20 malfunctions, as shown in FIG. 5, the rise time width t'3 of the supervisory signal WAT2 input to the computer 10 becomes longer than the normal value ta.

This change in the monitoring signal WAT2 is determined by the abnormality determination circuit 26 in FIG.
It is determined that the output exceeds the reference value, the output changes from L level to H level, and returns to L level again after a predetermined period of time.

Then, as is clear from FIG. 3, the output of the inverter 17 changes from the H level to the L level and returns to the H level again, and the output of the AND gate 16 changes similarly.

Therefore, when the output of the AND gate 16 changes from the L level to the H level, the abnormally operating computer 20 is reset in the same way as when the power is turned on.The abnormal operation of the computer 20 is recovered by initializing to the initial program. .

Of course, if the computer 10 malfunctions, the normally operating computer 20 will similarly issue a reset.

As explained above, the multi-computer device of the present invention is configured such that the computers in the multi-configuration mutually detect abnormal operations in other computers and reset them. Even if a problem occurs, a reset can be automatically applied to restore normal operation without having to reset the power by turning the power on again, and the operating rate of the multi-computer device can be further increased.

In addition, the operations that should detect abnormalities in each computer include an abnormality detection operation and a reset command operation, that is,
If you include the monitoring operation of other computers,
As for the monitoring operation itself, each computer monitors each other, and the reliability of the multi-computer system can be further increased.

Furthermore, in addition to recovering from an abnormality by resetting, by continuing to reset one computer to another computer, it is also possible to control the operation of the other computer to be prohibited as necessary.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a reset circuit of a conventional multi-computer device, FIG. 2 is a time chart diagram in the conventional example of FIG. 1, and FIG. 3 is a block diagram showing an embodiment of the present invention. 4 is a block diagram showing the internal circuit of the computer device shown in FIG. 3, FIG. 5 is a time chart diagram for the embodiment of FIG. 3, and FIG. 6 is a time chart diagram for the internal circuit of FIG. 4. be. 1.2,10,20... Computer, 3゜1
2...Power switch, 4,13...Timer circuit, 5.14...Waveform shaping circuit, 6...
...Buffer circuit, 11...DC power supply, 1
5, 16...and gate, 17, 18-...
---・Inverter, 21. 21a, 21b...
...Abnormality monitoring circuit, 22, 31...Interface, 23...Timer circuit, 24...
・Counter, 25... Setting device, 26...
・Abnormality judgment circuit.

Claims (1)

[Claims] 1. In a multi-computer device for a vehicle having a plurality of computers that execute independent program control in parallel, each of the computers has a determining means for determining that another computer has performed an erroneous calculation, and the determining means includes: 1. A multi-computer device for a vehicle, comprising means for causing another computer to perform recalculation when an erroneous calculation is determined.