JPH02234241A - Reset retry circuit - Google Patents

Abstract

PURPOSE:To obtain the hardware with high reliability by resetting automatically the intermittent errors and stopping the hardware if an error is immediately produced again even though an automatic resetting action is tried. CONSTITUTION:The normal working is monitored by a watchdog timer 13 and a parity checker 14. The timer 13 detects the runaway of an MPU, and the checker 14 detects the errors occurring on a data bus of the MPU. These errors are recovered by resetting the hardware. Then the working of a device is stopped as long as the error occurring interval is kept within a fixed time when the errors are continuously produced by the hard troubles, etc. Thus it is possible to obtain the hardware that does not easily have a down and has the high reliability.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to a microprocessor unit (hereinafter referred to as MPU).
The present invention relates to applied products, and in particular to a reset/retry method in the event of an error, which is suitable for control systems, protection systems, etc. of various systems that require high reliability.

[Conventional technology]

Conventionally, MPU application products have been designed to operate automatically when power is turned on or off, etc., as described in [Auto-reset circuit for digital circuits].
A method was adopted in which the hardware was reset if the power supply voltage was outside the rated range.

[Problem to be solved by the invention]

The above conventional technology does not take into consideration resetting in the event of an error that cannot be recovered without relying on a hardware reset, and for this reason, when an error occurs, the device must be brought down. There was a problem.

The purpose of the present invention is to prevent downtime due to intermittent errors by automatic recovery by hardware reset when an error occurs, and to prevent downtime due to an error caused by a truly fatal hardware failure. The purpose of this invention is to provide a retry circuit.

(Means for resolving llifi) The above purpose is to perform a hardware reset when an error that requires recovery by a hardware reset is detected, and when the error is caused by a hardware failure, etc. , if the error occurs continuously, this can be achieved by stopping the device when the error occurrence interval is within a certain period of time.

[Effect]

When an error requiring a hardware reset is detected, this method performs a hardware reset, allowing automatic recovery by starting a reset. As a result, if the error is intermittent, normal operation is possible from now on.

On the other hand, if the error is continuous due to a hardware failure, etc., the error will occur again even after automatic recovery by this operation. Depending on the method of stopping,
Shutdown is achieved only in truly fatal cases.

〔Example〕

An embodiment of the present invention will be described below.

FIG. 1 shows one embodiment of the invention.

This embodiment includes a watchdog timer 13 and a parity checker 14 for detecting errors that require hardware reset, a flip/flop 2 for recognizing the point at which an error occurs, and measuring the elapsed time from the point at which the error occurs. one-shot multi-vibrator 4 for resetting the hardware when an error occurs, one-shot 1/manoretic vibrator 9 for resetting the hardware when an error occurs, and stopping the hardware if an error occurs again within a certain period of time after the first error. Flip/Flop 5 for stopping
, and a reset circuit 15 for performing a normal hardware reset by checking the power supply voltage.

The operation of this embodiment will be explained below.

First, when the electric rX voltage is uncertain, such as when turning on or turning off the power,
The reset circuit 15 outputs a reset signal 7,
Reset equalizer number 11. is output and the hardware is reset.

During normal operation, the watchdog timer 13 and . The parity checker 14 monitors the runaway of the MPU, and the watchdog timer 13 monitors the runaway of the MPU.
It is necessary to detect the occurrence of an error on the data path of the PU, and to recover by hardware reset when any error occurs.

When any of these errors occurs, an error detection signal 1 is output, and the flip/flop 2 detects the point of occurrence, that is, the rising edge of the error detection signal 1. As a result, when the error signal 3 is output, the one-shot multivibrator 4 is triggered, and the reset activation signal 6 is output for a preset one-shot time.

When the one-shot multivibrator 9 is triggered by the rising edge of this reset activation signal 6, an error reset signal 10 is output, and as a result, the reset signal Bl
1 is output and a hardware reset is performed.

As a result of the above, hardware reset is actually performed when an error occurs. On the other hand, once an error occurs, during the one-shot time when the reset start signal 6, which is the output of the one-shot multivibrator 4, is output due to the above operation, an error occurs again, and the error detection signal 1 When a rising edge occurs, the stop flip/flop 5 takes in the reset activation signal 6 and outputs the stop signal 12.

With the output of this stop signal 12, the stop flip/flop 5 is locked and the hardware is stopped.

This operation will be explained using the time chart shown in FIG.

When the error detection signal ``:'', 1 becomes active due to the occurrence of an error, the error signal 3 becomes active at its rising edge. When the reset activation signal 6 becomes active at the rising edge of the error signal 3, the reset signal Bll becomes active and the hardware is reset.

At the rising edge of the error detection signal 1, the level of the reset activation signal 6 is reflected in the stop signal 12, but at the time of the rising edge of the error detection signal 1, the reset activation signal 6 is low level, so the stop signal 12 is It remains high and the hardware runs again and recovers from the error when the reset signal 11 becomes inactive and the reset ends.

Here, the reset activation signal 6 is active (high level) for a one-shot time T, but once an error occurs, it automatically returns and during operation, t l>T
Even if an error occurs again after a time 1x such that
Since the reset activation signal 6 is already at low level,
The stop signal 12 remains at a high level and automatically returns after being reset again.

In this way, automatic recovery is possible in the case of an intermittent error caused by noise or the like that may occur sporadically.

On the other hand, when an error occurs due to a hardware failure, etc., it occurs frequently, so the error occurrence interval t 2 <
In this case, the high level of the reset activation signal 6, which has become active due to the previous error, becomes the stop signal 1 at the rising edge of the error detection signal 1.
As a result, no reset is performed and the hardware is stopped. In this way, for intermittent errors that occur rarely, it is possible to automatically recover by resetting, and even if you try to reset and automatically recover due to an error such as a hardware failure, if the error occurs again immediately, , the hardware can be stopped. According to this embodiment, in the case of an intermittent error that can be automatically recovered by a reset, a retry is possible by automatic recovery, and the one-shot multivibrator is used to isolate errors caused by truly fatal hardware failures. 4
Since it can be changed in a one-shot time setting, it can be easily optimized for various types of hardware, making it possible to realize highly reliable hardware that is less likely to go down.

〔Effect of the invention〕

According to the present invention, in the case of an intermittent error, the system automatically recovers by a reset start without going down, and is stopped only when the error occurs continuously or frequently, such as a truly fatal hardware failure. be able to.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a timing chart explaining the operation of FIG. 1. 2...Flip/flop, 4...One-shot multivibrator, 5...Flip/flop for stopping.

Claims (1)

[Claims] 1. In a microprocessor applied product, when an error that cannot be recovered without a hardware reset is detected, the hardware reset is performed;
A reset/retry circuit characterized in that the hardware is stopped when the error occurrence interval is within a certain period of time.