JPH0642209B2 - Information processing equipment - Google Patents

Description

The present invention relates to an information processing system.

[Conventional technology]

FIG. 2 shows a block diagram of a conventional one, in which the information processing unit 1 performs calculations and the like under the control of the control storage unit 4. Diagnostic control unit 2
Indicates the location of failure when the information processing unit 1 fails. The address register 3 always holds the address of the control storage unit 4 to be executed next. The control storage unit 4 is a memory having the address register 3 as an address, and its output controls a register, a selector, etc., which will be described later, to perform an operation or the like.

The flip-flop 7 holds the contents of the signal line 124 when the parity detection circuit 16 detects a failure, and when the diagnostic control unit 2 reads the contents, the selector 14 selects either the register 11 or the register 12 when the failure occurs. Is output.

Next, in order for the diagnostic control unit 2 to read the contents of the register 11 or the register 12 that caused the failure, the selector 14 stored in advance in the control storage unit 4 selects the address of the microinstruction for selecting the register 11, or Alternatively, the selector 14 sets the address of the microinstruction for selecting the register 12 in the address register 3 so that the register 11 or the register 12 is provided on the signal line 127.
Output and read the contents of. If the previously read value of the flip-flop 7 indicates the register 11 and the data in the register 11 is not correct, it can be seen that the cause of the parity detection circuit 16 reporting the error is in the register 11, and The value of 7 is register 1
If 1 is indicated and the data in the register 11 is correct, it can be understood that the cause of the fault lies in any of the signal line 125, the selector 14, the signal line 127, the parity detection circuit 16, and the signal line 128. The same applies when the value of the flip-flop 7 indicates the register 12.

As described above, in the conventional technique, when the number of registers is increased, the time and effort for setting the read path are increased, and the area of the control storage unit 4 is increased.

[Problems to be solved by the invention]

In the conventional information processing method described above, in the method of storing the data for setting the read path in the control storage unit in advance, the correctness of the stored data is not guaranteed at the time of executing the diagnosis, so that the content state is correct. Is not read, and if there is a large amount of data to be read, the amount of that data will also increase, and the area of the control storage section will be used more and the original microinstruction storage capacity will decrease. There are drawbacks such as.

Further, in order to write the data for setting the read path from the outside to the rewritable control storage unit and read the internal state, means for saving the original microinstruction and means for writing the one-word microinstruction from the outside are required. There is a drawback that

[Means for solving problems]

According to the present invention, a computing unit that receives a control signal to perform computation,
First register means and second register means for holding the calculation result of the arithmetic unit, and selector means for receiving the control signal and selecting the first register means or the second register means to send to the arithmetic unit A controlled circuit means including: a control storage unit for generating a control signal to the controlled circuit unit; two flip-flop means for holding the control signal generated by the control storage unit; Two different ones are sent to the controlled circuit means as a control signal for switching the selector means and as a control signal for controlling the arithmetic unit by switching each of the input and the output to the two flip-flop means. Information processing section including a selector means, a parity detection circuit for detecting an error in the output of the arithmetic unit, and an error output by the parity detection circuit. When the signal detects that a failure has occurred in the information processing unit, the updating of the two flip-flop means is suppressed, and the control signals held by the two flip-flop means are selected by the two different selector means. Thus, there is provided an information processing apparatus comprising: a diagnostic control unit for controlling the above-described control, and reading the internal state of the controlled circuit means when a failure occurs.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The information processing unit 1 performs calculations and the like under the control of the control storage unit 6. The diagnosis control unit 2 points out a failure location when the information processing unit 1 fails. The address register 3 always holds the address of the control storage unit 4 to be executed next. The microinstruction register 5 holds only one word of the microinstruction stored in the control storage unit 4. The control storage unit 6 is a memory that uses a part of the microinstruction register 5 as an address, and the output thereof controls a register, a selector, and the like, which will be described later, to perform an operation or the like.
When the parity detection circuit 16 detects an error, the flip-flops 7 and 8 hold the contents of the signal lines 104 and 105 so that the diagnostic control unit 2 can read the contents later, and the flow of data causes an error. This is to point out the faulty part by knowing whether it has occurred.

The first selectors 9 and 10 select the control storage unit 6 and the flip-flops 7 and 8 to control the controlled circuit. When the control storage unit 6 is selected, the contents of the microinstruction register 5 are selected. Then, the control storage unit 6 is accessed, and the contents are used to control the register and the selector to perform operations and the like. When the flip-flop as the path indicator is selected, the selector is controlled by the content of the flip-flop to open the read path and read the content of the register to the diagnostic control unit 2.

The first, second, and third registers 11, 12, and 13, the second selector 14, and the arithmetic unit 15 constitute a controlled circuit based on microinstructions, and perform movement between registers and arithmetic operations.

The parity detection circuit 16 includes registers 11, 12, and 13 shown in FIGS. 1, 2, and 3, a second selector 14, an arithmetic unit 15,
The parity check is performed by the parity bit attached to the data paths 112 to 116.

Next, the operation will be described. First, when the information processing unit 1 performs an operation or the like under the control of microinstructions, the diagnostic control unit 2 causes the signal lines 118 and 119 so that the first selectors 9 and 10 select the signal lines 105 and 104. To At that time, the control storage unit 4 is accessed by the microinstruction address indicated by the address register 3, and the microinstruction register 5 is set with one word of the microinstruction corresponding to the address. At that time, the output of the control storage unit 6 accessed by a part of the field of the micro instruction register 5 passes through the first selectors 9 and 10 to control the second selector 14 and the arithmetic unit 15, and
The signal lines 120 (three lines) directly control the first, second, and third registers 11, 12, and 13 to perform operations and the like.

At this time, when the parity detection circuit 16 detects an error and reports it to the diagnostic control unit 2, the diagnostic control unit 2 immediately holds the flip-flops 7 and 8 and the state of the signal lines 104 and 105 when the error is detected. Hold. Here, the diagnostic control unit 2 reads the states of the flip-flops 7 and 8 in preparation for pointing out a failure location later.

Next, the diagnostic control unit 2 connects the first selectors 9 and 10 to the signal line 1
When the flip-flops 7 and 8 as path indicators are set to appropriate values by selecting the 07 and 109 sides, the first selectors 9 and 10 are passed to control the second selector 14 and the arithmetic unit 15. However, the first, second, and third registers 11, 12, and 13 can be sequentially output onto the signal line 116, and they are read one after another. As a result, the signal lines 112 to 116, the arithmetic unit 15, the parity detection circuit 16, and the contents of the flip-flops 7 and 8 which are the previous path indicators and the contents of the first to third registers 11 to 13 are used. It is possible to know where in the first, second, and third registers 11 to 13 the failure has occurred.

〔The invention's effect〕

As described above, the present invention makes it possible to use a flip-flop that holds auxiliary information for pointing out a failure location as a control flip-flop for opening a path for reading the internal state, thereby reducing hardware. There is an effect that the ware can read the internal state without reducing the capacity of the control memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block showing an example of a conventional one. Explanation of symbols: 1 ... Information processing unit, 2 ... Diagnostic control unit, 3
... address register, 4 ... control storage unit, 5 ... microinstruction register, 6 ... control storage unit, 7, 8 ... flip-flop, 9, 10 ... first selector, 11, 1
2, 13 ... First, second and third registers, 14 ... Second selector, 15 ... Arithmetic unit, 16 ... Parity detection circuit.

Claims (1)

[Claims] Claim: What is claimed is: 1. An arithmetic unit for receiving a control signal to perform an operation, a first register means and a second register means for holding an operation result of the arithmetic unit, and a first register for receiving a control signal.
Of the register means or the second register means and sends it to the arithmetic unit, the controlled circuit means, the control storage part for generating a control signal to the controlled circuit means, and the control storage part. Holds the generated control signal 2
One flip-flop means and each of the inputs and outputs to the two flip-flop means are selected to serve as a control signal for switching the selector means and as a control signal for controlling the arithmetic unit. An information processing unit including two separate selector units for sending to the control circuit unit and a parity detection circuit for detecting an error in the output of the arithmetic unit, and an error signal output from the parity detection circuit causes a failure in the information processing unit. And a diagnostic control unit that controls the update of the two flip-flop units and controls the two separate selector units to select the control signals held by the two flip-flop units. An information processing apparatus, comprising: an internal state of the controlled circuit means when a failure occurs.