JPS57123461A - Error checking system - Google Patents
Error checking systemInfo
- Publication number
- JPS57123461A JPS57123461A JP56009031A JP903181A JPS57123461A JP S57123461 A JPS57123461 A JP S57123461A JP 56009031 A JP56009031 A JP 56009031A JP 903181 A JP903181 A JP 903181A JP S57123461 A JPS57123461 A JP S57123461A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- error
- register
- error check
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
PURPOSE:To decrease the number of error check circuits and error latch circuits, by selectively supplying plural register outputs to be a subject of error check to a common error check circuit and latching the error check results by a common latch circuit. CONSTITUTION:With the generation of a destination designating signal DES equal to an A-P signal, a selector circuit 35 selects the output of an A register 31 and supplies it to a parity check circuit 36. Then an error check timing signal Ti-P is produced, and accordingly the output of the circuit 36 is supplied to an error latch circuit 37 via an AND gate 39. Thus the parity check result of the register 31 is latched. The output signals ERi-P and ERj-P of the latch circuits 37 and 38 are supplied to a freezing control circuit 24. With the generation of either signal ERi-P or ERj-P, the circuit 24 preserves the contents of a data register 22. Thus it is possible to analyze the error factor due to a service processor 26.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56009031A JPS57123461A (en) | 1981-01-26 | 1981-01-26 | Error checking system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56009031A JPS57123461A (en) | 1981-01-26 | 1981-01-26 | Error checking system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57123461A true JPS57123461A (en) | 1982-07-31 |
JPS6321928B2 JPS6321928B2 (en) | 1988-05-10 |
Family
ID=11709278
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56009031A Granted JPS57123461A (en) | 1981-01-26 | 1981-01-26 | Error checking system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57123461A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61109154A (en) * | 1984-11-01 | 1986-05-27 | Fujitsu Ltd | Error detecting system for fixed data register |
JPS6332637A (en) * | 1986-07-26 | 1988-02-12 | Nec Corp | Information processing system |
-
1981
- 1981-01-26 JP JP56009031A patent/JPS57123461A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61109154A (en) * | 1984-11-01 | 1986-05-27 | Fujitsu Ltd | Error detecting system for fixed data register |
JPS6332637A (en) * | 1986-07-26 | 1988-02-12 | Nec Corp | Information processing system |
Also Published As
Publication number | Publication date |
---|---|
JPS6321928B2 (en) | 1988-05-10 |
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