JPS6486258A - Address bus testing system - Google Patents

Address bus testing system

Info

Publication number
JPS6486258A
JPS6486258A JP62243465A JP24346587A JPS6486258A JP S6486258 A JPS6486258 A JP S6486258A JP 62243465 A JP62243465 A JP 62243465A JP 24346587 A JP24346587 A JP 24346587A JP S6486258 A JPS6486258 A JP S6486258A
Authority
JP
Japan
Prior art keywords
address bus
circuit
address
unit
comparing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62243465A
Other languages
Japanese (ja)
Inventor
Masaaki Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62243465A priority Critical patent/JPS6486258A/en
Publication of JPS6486258A publication Critical patent/JPS6486258A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To detect a trouble in which a specific bit is fixed to either 0 or 1 by outputting 0 or 1 to all the bits of an address bus, storing it in them, instructing to set comparing data to either 0 or 1, and comparing the data. CONSTITUTION:At the time of testing the address bus, a central processing unit 1 reads a program for testing the address bus in a storing circuit 2, sets a 0 address to a register R in the unit 1, makes a comparing data signal 30 into 0, and makes gate signals 31 and 34 into 1 through an input and output control device 3. Next, the unit 1 impresses the output of a shift register circuit 4 loaded with an address on an address bus 17 in parallel and the comparing data signal 30 to an exclusive 'or' circuit 5, reads the condition of a result output signal 28 of an FF circuit 7 impressed the output signal, and decides the trouble.
JP62243465A 1987-09-28 1987-09-28 Address bus testing system Pending JPS6486258A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62243465A JPS6486258A (en) 1987-09-28 1987-09-28 Address bus testing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62243465A JPS6486258A (en) 1987-09-28 1987-09-28 Address bus testing system

Publications (1)

Publication Number Publication Date
JPS6486258A true JPS6486258A (en) 1989-03-30

Family

ID=17104293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62243465A Pending JPS6486258A (en) 1987-09-28 1987-09-28 Address bus testing system

Country Status (1)

Country Link
JP (1) JPS6486258A (en)

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