JPS6451536A - Output protector - Google Patents

Output protector

Info

Publication number
JPS6451536A
JPS6451536A JP62207496A JP20749687A JPS6451536A JP S6451536 A JPS6451536 A JP S6451536A JP 62207496 A JP62207496 A JP 62207496A JP 20749687 A JP20749687 A JP 20749687A JP S6451536 A JPS6451536 A JP S6451536A
Authority
JP
Japan
Prior art keywords
abnormality
signal
outputted
equipment
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62207496A
Other languages
Japanese (ja)
Inventor
Susumu Katsumata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62207496A priority Critical patent/JPS6451536A/en
Publication of JPS6451536A publication Critical patent/JPS6451536A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To prevent the outputting of erroneous data to an equipment by adding an abnormality decision circuit which decides the presence/absence of an abnormality based on a decision result outputted from a pattern decision circuit and a write signal, and providing a gate not to output a write signal to an equipment in case of abnormality occurring. CONSTITUTION:In case data is transferred from a computer 1 to an equipment 2, the computer 1 executes an output instruction. During this time, a write signal WR and an address signal ADD representing the destination of the data are outputted from the computer 1 in addition to a data signal DAT. First, whether the pattern of the data signal DAT coincides with a preliminarily-set pattern or not is decided by the pattern decision circuit 3, and a decision result is outputted to the abnormality decision circuit 4. The decision as to abnormality/normality is executed based on said result and a write signal WR, and in case of normality being decided on, a signal is transmitted to the gate 5 to open the gate 5, and the write signal WR is outputted to the equipment 2. In case of abnormality, the signal WR necessarily is not outputted to the equipment 2.
JP62207496A 1987-08-21 1987-08-21 Output protector Pending JPS6451536A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62207496A JPS6451536A (en) 1987-08-21 1987-08-21 Output protector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62207496A JPS6451536A (en) 1987-08-21 1987-08-21 Output protector

Publications (1)

Publication Number Publication Date
JPS6451536A true JPS6451536A (en) 1989-02-27

Family

ID=16540679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62207496A Pending JPS6451536A (en) 1987-08-21 1987-08-21 Output protector

Country Status (1)

Country Link
JP (1) JPS6451536A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05334110A (en) * 1992-06-04 1993-12-17 Nec Corp Delay error correcting device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05334110A (en) * 1992-06-04 1993-12-17 Nec Corp Delay error correcting device

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