JPS57137953A - Clock stop system - Google Patents
Clock stop systemInfo
- Publication number
- JPS57137953A JPS57137953A JP56023807A JP2380781A JPS57137953A JP S57137953 A JPS57137953 A JP S57137953A JP 56023807 A JP56023807 A JP 56023807A JP 2380781 A JP2380781 A JP 2380781A JP S57137953 A JPS57137953 A JP S57137953A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- inputted
- terminal
- exclusive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318552—Clock circuits details
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
PURPOSE:To stop a clock at the required time, by inputting an output of a logical circuit and an output of a signal polarity designating circuit, to one input terminal of an exclusive OR circuit and its other terminal, respectively, and detecting a difference between the logical circuit output and the signal polarity designating circuit output. CONSTITUTION:An output of a logical circuit 1 is divided into 2 branches, and one branch is inputted to a scan-out data register 4 through a flip-flop circuit 3 being a conventional circuit, and the other branch is inputted to one terminal of an exclusive OR circuit 10. A signal from a service processor (SVP) is inputted to a signal polarity designating circuit 11, and its output is inputted to the other terminal of the exclusive OR circuit 10. An output of the exclusive OR circuit 10 is inputted to one terminal of an AND circuit 13. To the other terminal of the AND circuit 13, an output of a flip-flop circuit 12 connected to the SVP is inputted. An output of the AND circuit 13 outputs a clock stop signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56023807A JPS57137953A (en) | 1981-02-20 | 1981-02-20 | Clock stop system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56023807A JPS57137953A (en) | 1981-02-20 | 1981-02-20 | Clock stop system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57137953A true JPS57137953A (en) | 1982-08-25 |
Family
ID=12120590
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56023807A Pending JPS57137953A (en) | 1981-02-20 | 1981-02-20 | Clock stop system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57137953A (en) |
-
1981
- 1981-02-20 JP JP56023807A patent/JPS57137953A/en active Pending
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