JPS57206961A - Logical integrated circuit - Google Patents

Logical integrated circuit

Info

Publication number
JPS57206961A
JPS57206961A JP56092505A JP9250581A JPS57206961A JP S57206961 A JPS57206961 A JP S57206961A JP 56092505 A JP56092505 A JP 56092505A JP 9250581 A JP9250581 A JP 9250581A JP S57206961 A JPS57206961 A JP S57206961A
Authority
JP
Japan
Prior art keywords
array
output signals
parity
optional
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56092505A
Other languages
Japanese (ja)
Inventor
Teruhiko Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56092505A priority Critical patent/JPS57206961A/en
Publication of JPS57206961A publication Critical patent/JPS57206961A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Abstract

PURPOSE:To simplify the check of troubles by checking the parity of each output signal from an AND array generating the AND of an output signal of a decoding circuit and an OR array generating an optional OR of the AND array. CONSTITUTION:An AND array 2 generates an optional AND of output signals of a decoding circuit 1 decoding external input signals. An OR array 3 generates optional OR of output signals of the AND array. A register circuit 4 controls the output signals of the AND array 2. Parity check circuits 51, 52, 53 check the parity of output signals of a decoding circuit 1, the AND array 2 and the OR array respectively. Troubles are checked by observing the output signals of the parity check circuits 51, 52, 53.
JP56092505A 1981-06-16 1981-06-16 Logical integrated circuit Pending JPS57206961A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56092505A JPS57206961A (en) 1981-06-16 1981-06-16 Logical integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56092505A JPS57206961A (en) 1981-06-16 1981-06-16 Logical integrated circuit

Publications (1)

Publication Number Publication Date
JPS57206961A true JPS57206961A (en) 1982-12-18

Family

ID=14056160

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56092505A Pending JPS57206961A (en) 1981-06-16 1981-06-16 Logical integrated circuit

Country Status (1)

Country Link
JP (1) JPS57206961A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990002450A1 (en) * 1988-08-31 1990-03-08 Fujitsu Limited Constitution for expanding logic scale of a programmable logic array
JP2544494B2 (en) * 1988-08-31 1996-10-16 富士通株式会社 Logical scale expansion configuration of programmable logic array

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990002450A1 (en) * 1988-08-31 1990-03-08 Fujitsu Limited Constitution for expanding logic scale of a programmable logic array
US5132570A (en) * 1988-08-31 1992-07-21 Fujitsu Limited Extended logical scale structure of a programmable logic array
JP2544494B2 (en) * 1988-08-31 1996-10-16 富士通株式会社 Logical scale expansion configuration of programmable logic array

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