JPS57157656A - Descrambler synchronizing circuit - Google Patents

Descrambler synchronizing circuit

Info

Publication number
JPS57157656A
JPS57157656A JP56042298A JP4229881A JPS57157656A JP S57157656 A JPS57157656 A JP S57157656A JP 56042298 A JP56042298 A JP 56042298A JP 4229881 A JP4229881 A JP 4229881A JP S57157656 A JPS57157656 A JP S57157656A
Authority
JP
Japan
Prior art keywords
shift register
signal
descrambler
specific bit
coincidence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56042298A
Other languages
Japanese (ja)
Other versions
JPS6254253B2 (en
Inventor
Keiichi Senoo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56042298A priority Critical patent/JPS57157656A/en
Publication of JPS57157656A publication Critical patent/JPS57157656A/en
Publication of JPS6254253B2 publication Critical patent/JPS6254253B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03828Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
    • H04L25/03866Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using scrambling

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To output a normal descrambler signal, by detecting a coincidence of a prescribed bit train of a shift register and the first specific bit train, and inputting the second bit train in parallel to a prescribed stage of the shift register. CONSTITUTION:An input signal 5 from a receiving signal input terminal 1 is inputted to a shift register 9. The shift register 9 shifts the receiving signal by a clock, and inputs logical states a1-am to a pattern detecting circuit 12. The pattern detecting circuit 12 outputs a coincidence signal 13 when the logical states a1-am of the shift register 9 have coincided with the first specific bit trains a1'-am'. The shift register 9 sets the second specific bit trains am+1'-an' to the register element by a parallel input control signal from a terminal 23.
JP56042298A 1981-03-25 1981-03-25 Descrambler synchronizing circuit Granted JPS57157656A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56042298A JPS57157656A (en) 1981-03-25 1981-03-25 Descrambler synchronizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56042298A JPS57157656A (en) 1981-03-25 1981-03-25 Descrambler synchronizing circuit

Publications (2)

Publication Number Publication Date
JPS57157656A true JPS57157656A (en) 1982-09-29
JPS6254253B2 JPS6254253B2 (en) 1987-11-13

Family

ID=12632116

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56042298A Granted JPS57157656A (en) 1981-03-25 1981-03-25 Descrambler synchronizing circuit

Country Status (1)

Country Link
JP (1) JPS57157656A (en)

Also Published As

Publication number Publication date
JPS6254253B2 (en) 1987-11-13

Similar Documents

Publication Publication Date Title
JPS57157656A (en) Descrambler synchronizing circuit
JPS5735417A (en) D/a converter
JPS5477533A (en) Signal generating device
JPS554178A (en) Information control system
JPS5799062A (en) Reception circuit for data transmission
ES8604375A1 (en) Circuit for regenerating periodic signals.
JPS57208752A (en) Sub-signal transmitting system
JPS5455141A (en) Diagnosing shift circuit
JPS56164429A (en) Cue system for multiplex synchronizing operation
JPS5621440A (en) Stuff synchronizing system
JPS6410391A (en) Condition change detecting device
JPS5698030A (en) Odd dividing circuit
AU565845B2 (en) Recognising a change in logic state in a channel of an n-bit-multiplex signal
JPS57166646A (en) Logical circuit
JPS5725744A (en) Interleaving circuit
JPS57137953A (en) Clock stop system
JPS5587201A (en) Double system controller
JPS57201936A (en) Integrated logical circuit
JPS5717236A (en) Detector for synchronism
SU627505A1 (en) Information receiver
JPS5761328A (en) Detection circuit of coincidence of changing point of two kinds of clock signal
JPS56111944A (en) Parallel-series converter circuit
JPS5595138A (en) Input data discrimination system of data input unit
JPS5419615A (en) Control system for input and output unit
JPS56131242A (en) Signal receiving circuit