JPS57157656A - Descrambler synchronizing circuit - Google Patents
Descrambler synchronizing circuitInfo
- Publication number
- JPS57157656A JPS57157656A JP56042298A JP4229881A JPS57157656A JP S57157656 A JPS57157656 A JP S57157656A JP 56042298 A JP56042298 A JP 56042298A JP 4229881 A JP4229881 A JP 4229881A JP S57157656 A JPS57157656 A JP S57157656A
- Authority
- JP
- Japan
- Prior art keywords
- shift register
- signal
- descrambler
- specific bit
- coincidence
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03828—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
- H04L25/03866—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using scrambling
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To output a normal descrambler signal, by detecting a coincidence of a prescribed bit train of a shift register and the first specific bit train, and inputting the second bit train in parallel to a prescribed stage of the shift register. CONSTITUTION:An input signal 5 from a receiving signal input terminal 1 is inputted to a shift register 9. The shift register 9 shifts the receiving signal by a clock, and inputs logical states a1-am to a pattern detecting circuit 12. The pattern detecting circuit 12 outputs a coincidence signal 13 when the logical states a1-am of the shift register 9 have coincided with the first specific bit trains a1'-am'. The shift register 9 sets the second specific bit trains am+1'-an' to the register element by a parallel input control signal from a terminal 23.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56042298A JPS57157656A (en) | 1981-03-25 | 1981-03-25 | Descrambler synchronizing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56042298A JPS57157656A (en) | 1981-03-25 | 1981-03-25 | Descrambler synchronizing circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57157656A true JPS57157656A (en) | 1982-09-29 |
JPS6254253B2 JPS6254253B2 (en) | 1987-11-13 |
Family
ID=12632116
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56042298A Granted JPS57157656A (en) | 1981-03-25 | 1981-03-25 | Descrambler synchronizing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57157656A (en) |
-
1981
- 1981-03-25 JP JP56042298A patent/JPS57157656A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6254253B2 (en) | 1987-11-13 |
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