JPS56164429A - Cue system for multiplex synchronizing operation - Google Patents

Cue system for multiplex synchronizing operation

Info

Publication number
JPS56164429A
JPS56164429A JP6818380A JP6818380A JPS56164429A JP S56164429 A JPS56164429 A JP S56164429A JP 6818380 A JP6818380 A JP 6818380A JP 6818380 A JP6818380 A JP 6818380A JP S56164429 A JPS56164429 A JP S56164429A
Authority
JP
Japan
Prior art keywords
gate
synchronizing
fast
circuits
multiplex
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6818380A
Other languages
Japanese (ja)
Inventor
Hatsuo Murata
Susumu Iwasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6818380A priority Critical patent/JPS56164429A/en
Publication of JPS56164429A publication Critical patent/JPS56164429A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Logic Circuits (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To make normal operation without switching a special operation mode, by making the multiplex synchronizing operation into complete multiplex constitution, through the addition of a synchronizing circuit at the output side of a fast-in and fast-out type CUE. CONSTITUTION:Fast-in and fast-out FIFO type CUEs 30, 31 and synchronizing circuits 40, 41 are provided between duplexed logical devices 10, 11 and 20, 21. The CUEs 30, 31 produces an output signal which takes the output signal of the devices 10, 11 as an input to other devices 20, 21. Further, the circuits 40, 41 are connected respectively at a synchronizing terminal, and the 1st and 2nd gate circuits and the shift register of serial parallel-out are provided in the circuits 40, 41. Further, the 1st gate circuit compares wither one of the outputs of the shift register with the synchronizing signal of the other systems, and when both the signals are read for display, the gate is opened. Moreover, the ready display signal is outputted with the 2nd gate for the 1st gate output for complete multiplexing.
JP6818380A 1980-05-22 1980-05-22 Cue system for multiplex synchronizing operation Pending JPS56164429A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6818380A JPS56164429A (en) 1980-05-22 1980-05-22 Cue system for multiplex synchronizing operation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6818380A JPS56164429A (en) 1980-05-22 1980-05-22 Cue system for multiplex synchronizing operation

Publications (1)

Publication Number Publication Date
JPS56164429A true JPS56164429A (en) 1981-12-17

Family

ID=13366406

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6818380A Pending JPS56164429A (en) 1980-05-22 1980-05-22 Cue system for multiplex synchronizing operation

Country Status (1)

Country Link
JP (1) JPS56164429A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60134366A (en) * 1983-12-21 1985-07-17 Hitachi Ltd Direct memory access address control system
JPS60168256A (en) * 1984-02-10 1985-08-31 Hitachi Ltd Address management system of various direct memory access
JPS60183666A (en) * 1984-03-02 1985-09-19 Hitachi Ltd Dma transfer control system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60134366A (en) * 1983-12-21 1985-07-17 Hitachi Ltd Direct memory access address control system
JPS60168256A (en) * 1984-02-10 1985-08-31 Hitachi Ltd Address management system of various direct memory access
JPS60183666A (en) * 1984-03-02 1985-09-19 Hitachi Ltd Dma transfer control system

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