JPS5590151A - Synchronous state display system of multiplex digital signal transmission line - Google Patents

Synchronous state display system of multiplex digital signal transmission line

Info

Publication number
JPS5590151A
JPS5590151A JP16228178A JP16228178A JPS5590151A JP S5590151 A JPS5590151 A JP S5590151A JP 16228178 A JP16228178 A JP 16228178A JP 16228178 A JP16228178 A JP 16228178A JP S5590151 A JPS5590151 A JP S5590151A
Authority
JP
Japan
Prior art keywords
transmission line
written
group
signals
synchronous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16228178A
Other languages
Japanese (ja)
Inventor
Tetsuhiro Nomura
Hiroaki Sato
Kenji Miyayasu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP16228178A priority Critical patent/JPS5590151A/en
Publication of JPS5590151A publication Critical patent/JPS5590151A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To reduce the scale of a display unit by displaying a transmission line in an abnormal synchronous state corresponding to groups or to transmission lines in a group. CONSTITUTION:A string of signals outputted from a synchronous-state supervisory circuit are sequentially written in shift register 12 through input terminal C1, selector 11 and OR gate 19. After synchronous-state display signals of transmission line No.0 of a group of order zero of respective primary-group transmission lines #0-#15 are all written, sybchronous-state display signals of primary-group transmission line No.1 are written in sequence. In this case, written signals of transmission line No.0 are read out in sequence from the final cell or register 12 and OR results with previously-written information are written through OR gate 19. Next, this information is transferred to shift register 13 and outputted to display output lines 21 #0-#15 and if transmission line No.0 of transmission line #1 would be abnormal, ''1'' is outputted to corresponding output line 21 #1. Among display output lines 23 No.0-NO.23 led from register 15, output ''1'' is sent out to 23 No.0.
JP16228178A 1978-12-27 1978-12-27 Synchronous state display system of multiplex digital signal transmission line Pending JPS5590151A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16228178A JPS5590151A (en) 1978-12-27 1978-12-27 Synchronous state display system of multiplex digital signal transmission line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16228178A JPS5590151A (en) 1978-12-27 1978-12-27 Synchronous state display system of multiplex digital signal transmission line

Publications (1)

Publication Number Publication Date
JPS5590151A true JPS5590151A (en) 1980-07-08

Family

ID=15751486

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16228178A Pending JPS5590151A (en) 1978-12-27 1978-12-27 Synchronous state display system of multiplex digital signal transmission line

Country Status (1)

Country Link
JP (1) JPS5590151A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5132216A (en) * 1974-09-13 1976-03-18 Nippon Electric Co Taju pcm sochinokanshihoshiki

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5132216A (en) * 1974-09-13 1976-03-18 Nippon Electric Co Taju pcm sochinokanshihoshiki

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