JPS5761355A - Data transmission circuit having checksum - Google Patents

Data transmission circuit having checksum

Info

Publication number
JPS5761355A
JPS5761355A JP13727780A JP13727780A JPS5761355A JP S5761355 A JPS5761355 A JP S5761355A JP 13727780 A JP13727780 A JP 13727780A JP 13727780 A JP13727780 A JP 13727780A JP S5761355 A JPS5761355 A JP S5761355A
Authority
JP
Japan
Prior art keywords
data
input
multiplexers
parallel
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13727780A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Komoda
Yoshiharu Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP13727780A priority Critical patent/JPS5761355A/en
Publication of JPS5761355A publication Critical patent/JPS5761355A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H04L1/0043—Realisations of complexity reduction techniques, e.g. use of look-up tables

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)

Abstract

PURPOSE:To simplify a shift circuit which converts parallel data into serial data, by installing multiplexers, with the same quantities as the bit number of data, having the same number of data input terminals as prallel data. CONSTITUTION:32-bit input parallel data is divided into 8 parallel data D1, D2,...D8 every 4b bits. Multiplexers which provide the same number of data input terminals as the number of data, i.e., 8 input multiplexers are provided by four pieces, same numbers of bits of respective data, and the output of each multiplexer is inputted to a shift resistor SR1 having parallel input and serial output. Therefore, 32-bit shift registors in conventional circuits are replaced with 4 MXs of 8 input multiplexers. The number of gate conversion elements is largely reduced.
JP13727780A 1980-09-30 1980-09-30 Data transmission circuit having checksum Pending JPS5761355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13727780A JPS5761355A (en) 1980-09-30 1980-09-30 Data transmission circuit having checksum

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13727780A JPS5761355A (en) 1980-09-30 1980-09-30 Data transmission circuit having checksum

Publications (1)

Publication Number Publication Date
JPS5761355A true JPS5761355A (en) 1982-04-13

Family

ID=15194907

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13727780A Pending JPS5761355A (en) 1980-09-30 1980-09-30 Data transmission circuit having checksum

Country Status (1)

Country Link
JP (1) JPS5761355A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60196027A (en) * 1984-03-19 1985-10-04 Tsubakimoto Chain Co Time-division multiplex transmission system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60196027A (en) * 1984-03-19 1985-10-04 Tsubakimoto Chain Co Time-division multiplex transmission system
JPH0546733B2 (en) * 1984-03-19 1993-07-14 Tsubakimoto Chain Co

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