JPS6476319A - Data arranging circuit - Google Patents
Data arranging circuitInfo
- Publication number
- JPS6476319A JPS6476319A JP62235126A JP23512687A JPS6476319A JP S6476319 A JPS6476319 A JP S6476319A JP 62235126 A JP62235126 A JP 62235126A JP 23512687 A JP23512687 A JP 23512687A JP S6476319 A JPS6476319 A JP S6476319A
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- input
- stage
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- Image Processing (AREA)
Abstract
PURPOSE:To segment data at a high speed by arranging the selection circuits at (n) stages of a network to connect them together with specification of the outputs of those selection circuits and at the same time using a register which holds the selection signals of the selection circuits together with a mask pattern and an AND circuit set at the output of the final stage. CONSTITUTION:An n-stage network is formed between 2<n> pieces of input and 2<n> pieces of output and 2<n> pieces of 2-input/1-output selection circuits 201 are arranged at the (n) stages respectively. Then the j-th output of the (i-1)-th stage and the output of the (i+2<i-1>)mad2<2>-th component element are connected to the j-th two input signals (a) and (b) of the i-th stage respectively. A register 200 of 2<n> bits holds a selection signal (e) of the input signal of the circuit 201. At the same time, an optional 2<n>-bit mask pattern and an AND circuit 300 are set at the output of the final stage of the circuit 201. A mask pattern is supplied to the circuit 300 of the final stage as soon as data are read out. Thus the input data are arrayed. As a result, data can be segmented at a high speed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62235126A JPS6476319A (en) | 1987-09-18 | 1987-09-18 | Data arranging circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62235126A JPS6476319A (en) | 1987-09-18 | 1987-09-18 | Data arranging circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6476319A true JPS6476319A (en) | 1989-03-22 |
Family
ID=16981438
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62235126A Pending JPS6476319A (en) | 1987-09-18 | 1987-09-18 | Data arranging circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6476319A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0314023A (en) * | 1989-06-12 | 1991-01-22 | Tokyo Electric Co Ltd | Data input device for barrel shifter |
US10636625B2 (en) | 2013-09-03 | 2020-04-28 | Lam Research Corporation | System for coordinating pressure pulses and RF modulation in a small volume confined process reactor |
-
1987
- 1987-09-18 JP JP62235126A patent/JPS6476319A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0314023A (en) * | 1989-06-12 | 1991-01-22 | Tokyo Electric Co Ltd | Data input device for barrel shifter |
US10636625B2 (en) | 2013-09-03 | 2020-04-28 | Lam Research Corporation | System for coordinating pressure pulses and RF modulation in a small volume confined process reactor |
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