JPS57111667A - Data processing circuit - Google Patents
Data processing circuitInfo
- Publication number
- JPS57111667A JPS57111667A JP18705180A JP18705180A JPS57111667A JP S57111667 A JPS57111667 A JP S57111667A JP 18705180 A JP18705180 A JP 18705180A JP 18705180 A JP18705180 A JP 18705180A JP S57111667 A JPS57111667 A JP S57111667A
- Authority
- JP
- Japan
- Prior art keywords
- data
- buses
- byte
- transfer
- section data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Complex Calculations (AREA)
Abstract
PURPOSE:To transfer data, which has multiple data format like doubled-precision floating-point data and fixed-point data, through a less number of buses by using the same aligning circuit. CONSTITUTION:At the high-order digit parts and low-order digit parts of input registers IR-0-IR-3, split input section data MI-0-MI-7 are provided, and their outputs are transferred to output section data M0-1, M0-3, M0-5, and M0-7. An aligning circuit 3 requires only 32 buses for 4-byte data transfer between the section data. For 8-byte data transfer, output section data M0-0, M0-2, M0-4, and M0--6 are provided, and between those data and said input section data MI-0, MI-2, MI-4, and MI-6, 4 4-byte buses each, i.e. 16 buses in all are required. Consequently, the aligning circuit 3 manages with 52 buses for 4-byte transfer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18705180A JPS57111667A (en) | 1980-12-27 | 1980-12-27 | Data processing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18705180A JPS57111667A (en) | 1980-12-27 | 1980-12-27 | Data processing circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57111667A true JPS57111667A (en) | 1982-07-12 |
JPS6122831B2 JPS6122831B2 (en) | 1986-06-03 |
Family
ID=16199308
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18705180A Granted JPS57111667A (en) | 1980-12-27 | 1980-12-27 | Data processing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57111667A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009126243A (en) * | 2007-11-20 | 2009-06-11 | Honda Motor Co Ltd | Suspension device |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0742333A (en) * | 1993-08-02 | 1995-02-10 | Nippon Paper Ind Co Ltd | Handrail of stairs |
-
1980
- 1980-12-27 JP JP18705180A patent/JPS57111667A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009126243A (en) * | 2007-11-20 | 2009-06-11 | Honda Motor Co Ltd | Suspension device |
Also Published As
Publication number | Publication date |
---|---|
JPS6122831B2 (en) | 1986-06-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0171595A3 (en) | Floating point arithmetic unit | |
JPS57111667A (en) | Data processing circuit | |
JPS5438199A (en) | Calculation board | |
JPS5748141A (en) | Address conversion system | |
IT8721201A0 (en) | ASYNCHRONOUS REGISTER WITH MULTIPLE INPUT. | |
GB1087455A (en) | Computing system | |
JPS57114957A (en) | Interface system between central processing device and main storage device | |
ES8201330A1 (en) | A redundant computer system (Machine-translation by Google Translate, not legally binding) | |
JPS54104249A (en) | Trigonometric function computer | |
DE3572551D1 (en) | Circuit arrangement for the instruction-dependent calculation of operand addresses and for checking the page boundary crossing at operands for logical or decimal storage-to-storage instructions | |
JPS57121749A (en) | Fraction computer | |
JPS5696369A (en) | Vector element conversion processing system | |
JPS6474616A (en) | Processor | |
FR2421441A1 (en) | Information shunting system for digital processor - uses two registers and code lines between individual storage cells | |
JPS55119739A (en) | Binary-decimal conversion system | |
JPS643734A (en) | Multiplication circuit | |
JPS54159832A (en) | Adder and subtractor for numbers different in data length | |
JPS5569849A (en) | Multiplication control system | |
GB847996A (en) | Arithmetic circuitry | |
JPS5298443A (en) | Small computer | |
JPS6413624A (en) | Multiplication remainder arithmetic unit | |
GB1422322A (en) | Binary processor | |
JPS56135255A (en) | Error detection system for pipeline arithmetic device | |
JPS5694469A (en) | Pipeline processing device provided with linkage bus | |
JPS54162431A (en) | Arithmetic control unit |