JPS56135255A - Error detection system for pipeline arithmetic device - Google Patents

Error detection system for pipeline arithmetic device

Info

Publication number
JPS56135255A
JPS56135255A JP3799580A JP3799580A JPS56135255A JP S56135255 A JPS56135255 A JP S56135255A JP 3799580 A JP3799580 A JP 3799580A JP 3799580 A JP3799580 A JP 3799580A JP S56135255 A JPS56135255 A JP S56135255A
Authority
JP
Japan
Prior art keywords
latches
shift register
constitution
error
arithmetic stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3799580A
Other languages
Japanese (ja)
Inventor
Hideo Miyanaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3799580A priority Critical patent/JPS56135255A/en
Publication of JPS56135255A publication Critical patent/JPS56135255A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation

Abstract

PURPOSE:To cope with the occurrence of an error, by shifting error report information, generated in the processing of an arithmetic stage, in the shift register constitution of error report latches, the arithmetic stage name information in the shift register constitution of arithmetic stage name latches. CONSTITUTION:Error report latches 3-0-3-4 and arithmetic stage name latches 4-0-4-3 that correspond to arithmetic stages 1-0-1-3 are provided in groups, and latches 3-0-3-4 are coupled at least into shift register constitution. Further, latches 1-0-1-3 are coupled at least into shift register constitution; error report information generated in the processing of either arithmetic stage is shifted or circulated in the shift register constitution of latches 3-0-3-4, and error occurrence arithmetic stage information is also shifted or circulated in the shift register constitution of latches 1-0-1-3. Thus, the error occurrence state of each arithmetic stage is left as hysteresis information to cope with the error occurrence accurately.
JP3799580A 1980-03-25 1980-03-25 Error detection system for pipeline arithmetic device Pending JPS56135255A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3799580A JPS56135255A (en) 1980-03-25 1980-03-25 Error detection system for pipeline arithmetic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3799580A JPS56135255A (en) 1980-03-25 1980-03-25 Error detection system for pipeline arithmetic device

Publications (1)

Publication Number Publication Date
JPS56135255A true JPS56135255A (en) 1981-10-22

Family

ID=12513148

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3799580A Pending JPS56135255A (en) 1980-03-25 1980-03-25 Error detection system for pipeline arithmetic device

Country Status (1)

Country Link
JP (1) JPS56135255A (en)

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