JPS5696369A - Vector element conversion processing system - Google Patents
Vector element conversion processing systemInfo
- Publication number
- JPS5696369A JPS5696369A JP17220579A JP17220579A JPS5696369A JP S5696369 A JPS5696369 A JP S5696369A JP 17220579 A JP17220579 A JP 17220579A JP 17220579 A JP17220579 A JP 17220579A JP S5696369 A JPS5696369 A JP S5696369A
- Authority
- JP
- Japan
- Prior art keywords
- data
- registers
- bits
- register
- conversion processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Complex Calculations (AREA)
Abstract
PURPOSE:To enhance processing speed, by reading and processing respective sets of plural element data and plural mask bits. CONSTITUTION:Plural element data (b) and mask bits (m) in the vector register are read as one unit in one cycle of the conversion processing. Registers 3-0 and 3-1 where data (b) is set, register 4 where contents of one of these registers are held temporarily, registers 6-0 and 6-1 where plural element data (a) of the conversion result are set, and an align processing circuit provided with the gate which transfers contents of registers 3 and 4 to register 6 are provided, and bits (m) are utilized to generate gate control signals in 7-13, and data (b) is converted to data (a) corresponding to bits (m).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17220579A JPS6019825B2 (en) | 1979-12-28 | 1979-12-28 | Vector element conversion processing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17220579A JPS6019825B2 (en) | 1979-12-28 | 1979-12-28 | Vector element conversion processing method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5696369A true JPS5696369A (en) | 1981-08-04 |
JPS6019825B2 JPS6019825B2 (en) | 1985-05-18 |
Family
ID=15937527
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17220579A Expired JPS6019825B2 (en) | 1979-12-28 | 1979-12-28 | Vector element conversion processing method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6019825B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6072071A (en) * | 1983-09-28 | 1985-04-24 | Nec Corp | Vector processing device |
JPS60263268A (en) * | 1984-06-12 | 1985-12-26 | Nec Corp | Vector processor |
-
1979
- 1979-12-28 JP JP17220579A patent/JPS6019825B2/en not_active Expired
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6072071A (en) * | 1983-09-28 | 1985-04-24 | Nec Corp | Vector processing device |
JPH0310138B2 (en) * | 1983-09-28 | 1991-02-13 | Nippon Electric Co | |
JPS60263268A (en) * | 1984-06-12 | 1985-12-26 | Nec Corp | Vector processor |
JPH0325822B2 (en) * | 1984-06-12 | 1991-04-09 | Nippon Electric Co |
Also Published As
Publication number | Publication date |
---|---|
JPS6019825B2 (en) | 1985-05-18 |
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