JPS6019825B2 - Vector element conversion processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a vector-element conversion processing method, in particular, proposes element data bo, q, Q, etc. belonging to vector B, and converts mask bits corresponding to a given mask bit string. In the vector arithmetic unit that performs conversion processing on the element data that has been set up, the element data is read out in sets of multiple units to improve processing speed. This relates to a vector element conversion processing method.

Although the present invention is not necessarily limited to this, element data L, b, b2, . . . belonging to vector B
・In converting ■Element data bo, L
, b2..., vector compression processing that extracts data from part of the element data string D, as shown in FIG.
For example, mask bit string DATA2 corresponds to ATAI.
'B} element data is prepared, extracts only the element data with the mask bit set, and creates new element data DATA3 belonging to vector A, that is, ao, a,, a2... bo, q, b
2... to pre-specified element positions. In other words, as shown in FIG.・Distribute the data bo, b, b2... and create new element data DATA5 belonging to vector A, that is,
The process of creating a,,, etc. may be executed.

The purpose of the present invention is to execute the above processing at high speed.
It is an object of the present invention to provide a vector-element conversion processing method that improves processing speed by reading out q, b2, . . . as a set, and reading and processing a plurality of mask bits as a set.

For this purpose, the vector-element conversion processing method of the present invention is based on element data b belonging to vector B.
o, b, b2, etc. are interleaved and stored in a plurality of memory banks in a vector register, the above element data is sequentially read out, and conversion processing corresponding to the above elements is performed. Prepare mask bits that instruct whether or not to perform conversion processing on each element data corresponding to the element data stored in the vector register and/or the element data resulting from the above conversion processing. At the same time, the element datum, Q, b2... stored in the vector register and the mask
At least two bits are configured to be read out in a plurality of units within one cycle of the conversion process, and element data bo, b, Q... extracted from the vector register are set. An input data register, a holding register that temporarily holds the contents of at least one of the two data registers, and a conversion result storage register.
The data also comprises at least two output data registers in which a, a2... are set, and a gate for gating a transfer path for transferring the contents of the input data register and the holding register to the output data register. An align processing circuit is provided, and a gate control signal for turning on/off the gate of the align processing circuit is generated using the plurality of mysterious mask bits, and an input data register of the align processing circuit is generated. The element data bo, b, , Q... corresponding to the above mask bits are also set to a, a.
It is characterized by converting into 2... This will be explained below with reference to the drawings. FIG. 3 is an embodiment of the configuration of a vector register used in the present invention, and FIGS. FIG. 5 shows the configuration of an embodiment of the alignment processing circuit used in the present invention, FIG. 6 shows an example of vector compression processing, and FIG. 7 shows the configuration of the alignment processing circuit shown in FIG. 5 when the processing shown in FIG. 6 is performed. An explanatory diagram illustrating gate control. FIGS. 8A to 8L are explanatory diagrams showing the state of the gate control shown in FIG. 5 is an explanatory diagram illustrating gate control of the alignment processing circuit shown in FIG. 5 when the process shown in FIG. 9 is performed.

In Figure 3, 1-OE, 1-2E,...1-14
8 is an even number bank, 1-10, turtle-30,...1
-150 are odd number banks, #OVR, #IVR...
・#nVR is a vector register, and each vector register is positioned in an interleaved manner across the above-mentioned total of one bank, 2-0
2-3 are address registers which commonly supply address information to the four banks;
o, T, represent those that give the first half timing and the second half timing obtained by dividing one processing cycle into two.

One vector register, for example #OVR, is configured to store one vector, element data b〇, b, b2, . . . .

"For example, elements of element data.
Items with even numbers are allocated to even-numbered banks, and items with odd numbers are allocated to odd-numbered banks. Two banks, such as banks 1-OE and 1-2E, 1-10 and 1-30, etc., are paired and accessed at timings To and T, respectively. For this, for example bank 1-OE
The read data from the bank 1-28 and the issue data from the bank 1-28 are outputted at different times (of course, the same applies to the write, but is not shown). Therefore, in the configuration shown in FIG.
By giving address information as 0, 2-1, 2-2, 2-3, 2-0,..., 1
Corresponding to the contents of two address registers 2-0, data q from bank 1-OE and data b from bank 1-10 are output together, followed by data Q and data from banks 1-28. Data b3 from banks 1-30 are output together, and data A from the primary bank is output as b6 and 0 . . . .

Generally, data is output one after another as described above, but in the case of the present invention, the above-mentioned mask and
Depending on the format of the bit string, in some cases, the same band may be accessed repeatedly (in the case shown, it can be accessed), as shown by the arrow x in Figure 4B. A certain bank of silk (
Access may be delayed for 4 sets).

FIG. 5 shows "Fig. 1 and The configuration of an embodiment of the alignment processing circuit for executing the vector compression processing and vector expansion processing described with reference to this figure is shown.In the figure, 3-0 and 3-1 are input data registers, respectively, and 4 is a data holding Registers 5-0 and 5-1 are intermediate buffer registers, 6-0 and 6-1 are output data registers, ■, ■...016 are gates, and 7 is #I.
ROM address register, 8 is address conversion ROM,
9 is the #IROM output register, 10 is the #2ROM address.

Register, 1 1 is gate control information ROM, 1 2 is #
The fox OM output register 13 is a gate control information decoder, which turns on/off the gates ■, ■, ... according to the output signal.
Represents something to turn off. As explained with reference to FIGS. 1 and 2, mask bits are prepared corresponding to element data to be processed.

With this mask bit, for example, it is coarsened by 4 bits and #IR
The information set in the OM address register 7 and corresponding to the mask bit set set in the past is #IR.
Feedback from OM output register 9 and address conversion RO
This is the address information of M8.

Then, from the ROM8, the next gate control information ROMI
Address information corresponding to the first address for accessing I is read out. After the address information is set in the register 10, the ROM II is accessed, and gate control information as will be described later with reference to FIG. 7 is output to the register 12. Then, the address information of the address following the above-mentioned first address is set to register 01 from the register 12, and the gate control information is sequentially output. This gate control information is decoded by the decoder 13, and the gates ①, ②, . . . are turned on/off in accordance with the passage of time. Correspondingly, data from even-numbered banks is input to input data register 3.
-0, and the data from the odd bank is set in the input data register 3-1 and processed as shown in FIGS. 7 and 8.

Now, element data wide, b,? Mask bit 1111"1011,0111,0001,1 corresponding to...
111, .

That is, as shown in FIG. 6, the element date, q,
b2, wide and mask bit 1111 are first read;
The following element data b4, b5, wide, 0 and mask
Bits 1011, . . . 0 are sequentially read out. Then, it is processed by the alignment processing circuit shown in FIG. 5, and the element data ao, a as shown in the bottom row of FIG.
,,... are collected as data wide, q, Q, b3, wide, b6, b7, wide, b sail wide,, b, 5, 〇6... and stored in the vector register (Figure 3). It is being done. 7th
The figure shows that the decoder 1 shown in FIG.
3 shows which gate is turned on by the output signal from 3, and how which element data, b, . . . are transferred accordingly.

■, ■, ... in the figure correspond to the gates shown in Figure 5, and correspond to the logic "
1" indicates that it is turned on at a given timing, and E-READ and 0-READ are even-numbered banks. Represents read, odd bank read, RBE, RB
O1, . . . represent the registers shown in FIG.
Further, E-WRITE and 0-WRITE each represent a write. 0, 2, . . . in FIG. 7 correspond to element data bo, Q, b2, . . . 8A to L are timings to to t shown in FIG. 7,
．． An explanatory diagram showing the state of gate control up to now in association with the flow of data.

As can be seen from the figure, the element' data is b8, q2,
It can be seen that transfer of b.3 and q4 is stopped by gate control. The manner in which the gate control is performed is that which gates should be turned on are analyzed in advance from the state of the mask bit string and stored in the gate control information ROMI I in the form of a plurality of subroutines. You can think that.

In the illustrated embodiment, since the number of mask bits read at one time is four, it is obvious that there are patterns that can exist corresponding to one exposed mask bit, and which patterns are currently read. Whether a gate should be turned on is determined in relation to past mask bits.

For this reason, if you think about it for a moment, it is reasonable to assume that the manner in which the gate is turned on at the current point in time is that x selects one of the following.

However, the manner in which the gate is actually turned on and off is fixed, and it is sufficient to prepare a subroutine in advance as described above. FIG. 9 shows an example of vector expansion processing. Data after alignment can remain blank for element numbers whose bits are logical "0".

The element data processed in this way is transformed into a vector
When writing to the register, the element data of the vector that existed on the vector register, x, 2, x, 3, x, 7, x, 8, x
, 9 remain as they were, and the element data belonging to the new vector A heat, a., . . . as b. ,q,Q,wide,
Q, gon, wide, Q, gon, ... are obtained. In addition, the 9th
In the case of the illustrated processing, the same element data b8, b9, wide o, b, . are read out in duplicate, but it can be considered that the output from the decoder 3 shown in FIG. 5 controls the Andres register 2-2 shown in FIG. In addition, for the control corresponding to Y shown in FIG.
The same applies. The state of gate control corresponding to the process of FIG. 9 is shown in FIG.

Regarding the gate control in this case, it can be considered that the gate is controlled by the output from the decoder 13 shown in FIG. 5, based on the vector expansion process and the mask bit string. As described above, according to the present invention, it is possible to process a designated element at high speed by presenting and processing a plurality of element data at one time.

[Brief explanation of the drawing]

FIGS. 1 and 2 are explanatory diagrams each explaining aspects of processing executed by the present invention, FIG. 3 is an example configuration of a vector register used in the present invention, and FIGS. An explanatory diagram illustrating a manner in which element data is read from a vector register in the processing of the invention, FIG. 5 is an example configuration of an alignment processing circuit used in the invention,
6 is an example of vector compression processing, and FIG. 7 is an explanatory diagram illustrating gate control of the alignment processing circuit shown in FIG. 5 when the processing shown in FIG. 6 is performed. An explanatory diagram showing the state of the gate control shown in the figure in correspondence with the flow of data, FIG. 9 is an example of vector expansion processing, and FIG. 10 is the alignment shown in FIG. 5 when the process shown in FIG. 9 is performed. An explanatory diagram illustrating gate control of a processing circuit is shown. In the figure, 1-OE, 1-28, ... are even-numbered banks, 1-10, 1-30, ... are odd-numbered banks, #
OVR, #IVR, ... are vector registers, respectively.
2-0, 2-3 are address registers, 3-0 and 3-1 are input data registers, 4 is a data holding register, 6-0 and 6-1 are output data registers, 8 is address conversion ROM, 11 is gate control information R
OM, 13 represents a decoder. nera korez 櫨na a mother size 4 koi 8 lower 8 tog to recommended size 0 koburo ro 8 lower

Claims (1)

[Claims] 1 Element data b_0,b belonging to vector B
In a vector arithmetic device that sequentially reads the element data from a vector register in which _1, b_2, etc. are interleaved and stored in a plurality of memory banks and performs a conversion process corresponding to the element, the data is stored in the vector register. In addition to preparing a mask bit corresponding to the stored element data and/or the element data as a result of the conversion process, which instructs whether or not to perform the conversion process on each element data, The element data b_0, b_1, b_2, etc. stored in the vector register and the mask bit are read out in units of a plurality of units within one cycle of the conversion process, and the data is read out from the vector register. Read element data b_0, b_1, b_
2... are set to at least two input data registers and at least one of the two data registers.
At least two output data registers in which element data a_0, a_1, a_2, etc. of conversion results are set; and the contents of the input data register and the holding register are transferred to the output data register. and a gate that gates a transfer path for transferring the data to the data, and generates a gate control signal that turns on and off the gate of the alignment processing circuit using the plurality of read mask bits. Element data b_0, b_1 generated and set in the input data register of the alignment processing circuit
, b_2, . . . into element data a_0, a_1, a_2, . . . corresponding to the mask bits.