JPH0285948A - Direct memory access system - Google Patents

Abstract

PURPOSE:To improve the overall processing efficiency of a system by starting a direct memory access (DMA) control circuit after storing the information instructed by an instruction means into a memory means of the DMA control circuit via a processor and then completing the transfer of data between an input/output device and a memory with no second intervention of the processor. CONSTITUTION:An instruction means 7 gives an instruction to a processor 5 to store the information into a memory means 8 of a DMA control circuit 6 so that plural data blocks are transferred between an input/output device 4 and a memory 2. Then a control means 9 uses the information stored in the means 8 of the circuit 6 to transfer plural data blocks stored in the device 4 to the memory 2 and to store plural data blocks received from the memory 2 into the device 4. Thus the processor 5 starts the circuit 6 just in one time and does not need any more intervention any more. As a result, the load of the processor 5 is reduced and the overall processing efficiency of a system is improved.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Actions Examples Effects of the Invention [Summary] Data between memory and input/output devices This is a system that executes data transfer in direct memory access mode, with the aim of reducing the burden on the processor and increasing the processing efficiency of the entire system. In a system that includes a processor, a memory, an input/output device that transfers data to the memory, and a direct storage access control circuit that controls data transfer between the memory and the input/output device based on information set by the processor, The access control circuit includes a storage unit that stores information for transferring multiple data blocks between the input/output device and the memory, and a storage unit that stores information for transferring multiple data blocks between the input/output device and the memory based on the information stored in the storage unit. A control means for controlling block transfer is provided, and the processor is instructed to instruct the storage means provided in the direct memory access control circuit to store information for transferring a plurality of data blocks between the input/output device and the memory. After the processor stores the information instructed by the instruction means in the storage means of the direct write access control circuit and starts the direct memory access control circuit, input/output is performed without the processor's intervention again. The configuration is such that data transfer between the device and the memory is completed.

[Industrial application field]

The present invention relates to a system that transfers data between a memory and an input/output device using a direct memory access (hereinafter abbreviated as DMA) mode, and particularly when transferring a plurality of data blocks between an input/output device and a memory. The present invention relates to a direct storage access control method in which data transfer is completed with a single intervention by a processor.

In a system operating in DMA mode, for example, when transferring data between memory and input/output devices,
When the processor activates the DMA control circuit, data transfer is thereafter executed under the control of the DMA control circuit without requiring intervention by the processor.

By the way, multiple data blocks can be transferred from the memory side to the input/output device side with one intervention by the processor, and the input/output device side can combine them into one data block, but the input/output device side can be transferred only once by the processor. Since only one data block can be transferred to the memory side with the intervention of processor intervention is required at each time, but it is desirable that this intervention not be necessary.

[Conventional technology]

FIG. 4 is a block diagram illustrating the conventional technique, and FIG. 5 is a diagram illustrating the operation of FIG. 4.

The processor 1 sets the start address of the table provided in the memory 2 and the address of the input/output device 4 in the internal register of the DMA control circuit 3, and determines the number of data blocks to be transferred to the memory 2, their addresses, the number of words to be transferred, etc. After setting the recorded table, the DMA II control circuit 3 is activated.

The activated DMA control circuit 3 refers to the start address of the table of the memory 2 set in the internal register and the address of the input/output device 4, indexes the table set in the memory 2, and searches the table that exists in the memory 2. When the number of data blocks to be transferred, their addresses, and the number of words to be transferred are recognized, or the number of data blocks to be stored in memory 2, the start address of the memory area to be stored, and the number of words to be transferred, the process starts from the specified address in memory 2. Read a specified number of data blocks and transfer them to the input/output device 4, or
A data block from the input/output device 4 is read out, transferred to the memory 2, and stored in a designated address area.

Conventionally, the DMA control method for one boat of the DMA control circuit 3 is to transfer one data block from the memory 2 side to the input/output device 4 side, or to transfer one data block from the input/output device 4 side, as shown in FIG. 5(a). In the case of transferring multiple data blocks from the memory 2 side to the input/output device 4 side, as shown in FIG. There is a case where one data block is stored in a buffer memory of No. 4, one data block is transferred from the input/output device 4 side to the memory 2 side, and the data block is divided and stored in a designated address area of the memory 2.

[Problem to be solved by the invention]

As mentioned above, conventionally, multiple data blocks can be transferred from the memory 2 side with one intervention of the processor, but one data block can be transferred from the input/output device 4 side with one intervention of the processor. It is not possible to transfer multiple data blocks.

However, in recent years, the number of data blocks on the input/output device 4 side has been increasing due to increases in memory capacity and the like. Therefore, in the conventional method, when data transfer is performed for multiple data blocks to be transferred from the input/output device 4 side, D
Activation of the processor 1 to the MA II control circuit 3 is not completed in one go, and it is necessary to activate the DMA control circuit 3 in accordance with the number of data blocks to be transferred from the input/output device 4 side.

That is, when the processor 1 starts up the DMA control circuit 3, the processor 1 stores the start address of the table provided in the memory 2 and each buffer memory of the input/output device 4 in the internal register of the DMA control circuit 3. It is necessary to set the address of the data block storage area and to set a table in the memory 2 in which the number of data blocks, their addresses, and the number of transferred words are recorded.

Further, the same is true when multiple data blocks transferred from the memory 2 side are divided into multiple data blocks and received on the input/output device 4 side, which places a large burden on the processor l.
There is a problem in that the processing efficiency of the entire system is reduced.

In view of these problems, the present invention is designed so that the DMA control circuit 3 of the processor 1 only needs to be activated once, regardless of the number of data blocks on the input/output device 4 side, thereby reducing the burden on the processor 1 and reducing the load on the entire system. The aim is to increase processing efficiency.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

The same reference numerals as in FIG. 4 indicate the same functions. Based on instructions from the instruction means 7, the processor 5 stores information for transferring a plurality of data blocks between the input/output bag W4 and the memory 2 in the storage means 8 of the DMA control circuit 6. and,
A start signal is sent to the DMA control circuit 6.

Under the control of the control means 9, the DMA control circuit 6 starts operating in response to an activation signal sent from the processor 5, and reads out information stored in the storage means 8.

The information stored in the storage means 8 is stored in the input/output device 4, for example.
The number of data blocks to be transferred from or stored in the input/output device 4 and the address of the table provided in the memory 2.
The control means 9 of the DMA control circuit 6 uses this information to control the memory 2.
The address and number of transferred words of each data block are read out from the table provided in the memory 2.
and the input/output device 4.

That is, the control means 9 learns the number of data blocks and their addresses from the table provided in the storage means 8 and the memory 2, outputs data blocks one after another from the input/output device 4, and transfers data corresponding to the number of transfer words to the memory 2. , as explained in Figure 4,
Referring to the table provided in the memory 2, write to the specified address area of the memory 2, or read the data block of the memory 2, transfer data for the number of transfer words to the input/output device 4, and write the table. The data is written to the address area of the buffer memory of the input/output device 4 indicated by the address indexed from.

[Effect]

With the above configuration, the instruction means 7 instructs the processor 5 to transfer information for transferring a plurality of data blocks between the input/output device 4 and the memory 2 to the storage means 8 of the DMA control circuit 6. The control means 9 stores the DMA
Using the information stored in the storage means 8 of the i-control circuit 6, a plurality of data blocks existing in the input/output device 4 are transferred to the memory 2, and the plurality of data blocks transferred from the memory 2 are transferred to the input/output device. 4, the processor 5
The DMA control circuit 6 only needs to be activated once, and there is no need to intervene after that, reducing the burden on the processor 5, thereby increasing the processing efficiency of the system.

〔Example〕

FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention.
FIG. 3 is a diagram illustrating the operation of FIG. 2.

The processor 5 reads the program 23 and, according to the instructions of this program, first creates a table for storing transfer information in the memory 2 via the bus 24.

FIG. 3(a) shows the case of operation in the array chain mode, in which there are, for example, four data blocks to be transferred or stored in the memory 2 as shown in (■) to (■), and the input/output device 4 is Assume that there are three data blocks to be transferred or data blocks to be stored as shown in (1) to (2).

The processor 5 creates tables X and Y in the memory 2, as shown in FIG. (1) to [phase], the start address of each block area of data blocks (1) to (2) (hereinafter referred to as device address), and the number of transfer words (2) to 0 are set in table Y.

Then, the processor 5 controls the main control section 10 of the DMA control circuit 6 via the bus 24, causes the table address register 18 to set the start address of the table X provided in the memory 2 via the bus control section 11, and blocks The number of data blocks to be transferred (4 in this example) is set in the count register 20, and the table Y provided in the memory 2 is sent to the table address register 19 via the bus control unit 22.
The number of data blocks to be transferred (3 in this example) is set in the block count register 21.

Here, the processor 5 instructs the main control unit 10 to start up. The main control unit 10 that has been instructed to start uses the table X stored in the table address register 18 via the bus control unit 11.
The bus controller 22 reads the start address of the block count register 20 and the number of data blocks stored in the block count register 20.
The start address of table Y stored in the table address register 19 via the block count register 21
Reads the number of data blocks stored by.

The main storage unit 10 accesses the memory 2 using the start addresses of tables X and Y read from the table address registers 18 and 19, reads the contents of tables X and Y in the memory 2, and writes the memory address ,
The number of transferred words ■ is stored in the word count register 14 , the device address ■ is stored in the address register 13 , and the number of transferred words ■ is stored in the word count register 15 .

When transferring a data block from the memory 2 to the input/output device 4, the main control unit IO sequentially transfers the data block ■ of the memory 2 at the address specified by the memory address ■, and transfers the data block ■ to the bus 2.
4, and is stored in the buffer memory area (2) specified by the device address (2) of the input/output device 4. Here, the number of transferred words■
If and ■ are the same, the entire data block ■ is transferred to the area indicated by the data block ■.

Next, the main control unit 10 stores the memory address ■ in the address register 12, the number of transferred words ■ in the word count register 14, the device address @ in the address register 13, and the number of transferred words @ in the word count register 15.

Then, the data block (2) is successively generated at the address specified by the memory address (2) and stored in the buffer memory area (2) specified by the device address @ of the input/output device 4 via the bus 24. Here, if the number of transferred words ■ and @ are the same, the entire data block ■ is transferred to the area indicated by the data block ■.

Next, the main control unit 10 stores the memory address ■ in the address register 12, the number of transferred words ■ in the word count register 14, the device address 0 in the address register 13, and the number of transferred words 0 in the word count register 15.

Then, the data block (2) is successively generated at the address specified by the memory address (2) and stored in the sofa memory area (2) specified by the device address 0 of the input/output device 4 via the bus 24.

Here, since the number of transferred words ■ is less than 0, the data block ■ is all transferred to the area indicated by the data block ■, but the main control unit 10
I am aware of the difference in the number of data pro ivy stored in 1.
Since one more data block is transferred from the memory 2, the starting address in the buffer memory area (2) for storing the next data block is recognized from the difference between the number of transferred words 0 and (2).

Then, the main control unit 10 stores the memory address [phase] in the address register 12 and the number of transfer words [phase] in the word count register 14, and successively sends data blocks ■ at the address specified by the memory address [phase]. The data is stored in the buffer memory area (2) of the input/output device 4 via the storage device 24.

Here, if the number of transferred words 0 and the number of transferred words ■+[phase] are the same, data blocks ■ and ■ are all transferred to the area indicated by data block ■.

When transferring a data block from the input/output device 4 to the memory 2, the main control unit 10 reads the contents of tables X and Y,
Store the memory address ■ in the address register 12, the number of transferred words ■ in the word count register 14, store the device address 0 in the address register 13, and store the word count register 1.
The number of transferred words ■ is stored in 5.

Then, the data block (2) in the buffer memory area of the input/output device 4 specified by the device address 0 is sequentially output and stored in the area (2) of the memory 2 specified by the memory address (2) via the bus 24. Here, if the number of transferred words ■ and ■ are the same, the data block ■ is entirely transferred to the area indicated by the data block ■.

Next, the main control unit 10 reads the contents of tables X and Y, stores the memory address ■ in the address register 12, the number of transferred words ■ in the word count register 14, the device address 0 in the address register 13, and the word count register 15.
The number of transferred words [phase] is stored in .

Then, the data block (2) is successively output from the buffer memory area of the input/output device 4 specified by the device address @, and stored in the area (2) of the memory 2 specified by the memory address (2) via the bus 24. Here, if the number of transferred words ■ is equal to 0, the entire data block ■ is transferred to the area indicated by the data block ■.

Next, the main control unit 10 stores the memory address ■ in the address register 12, the number of transferred words ■ in the word count register 14, the device address 0 in the address register 13, and the number of transferred words 0 in the word count register 15.

Then, the data block ■ of the input/output device 4 specified by the device address ■ is sequentially output and transferred to the area ■ of the memory 2 specified by the memory address ■. The difference in the number of data blocks is recognized, and when data with the same number of words as the number of transferred words is transferred, the memory address [phase] is stored in the address register 12 and the number of transferred words [phase] is stored in the word count register 14. , the remaining data of the data block ■ is stored in the area ■ of the memory 2 specified by the memory address [phase].

Here, if the number of transferred words 0 and the number of transferred words ■+[phase] are the same, the data block ■ is entirely transferred to the areas shown in the data blocks ■ and ■.

Further, the main controller 10 stores DMA control start, stop, error information, etc. in the channel control registers 16 and 17, and performs the above operations.

FIG. 3(b) shows the case of operation in the link array chain mode, and similarly to FIG. 3(a), the data block to be transferred or the data block to be stored is stored in the memory 2.
It is assumed that there are four blocks as shown in .about.--■, and that there are three data blocks to be transferred or stored in the input/output device 4 as shown in .--.

Processor 5 creates tables X and Y in memory 2, and table X contains the memory addresses of data blocks ■～■,
Set the number of transferred words and link address ■~[phase] and the mesori address, number of transferred words, and table end code O of data block ■, and set the device address, number of transferred words, and link address @~ of data block ■~■ in table Y. [
Set the device address, number of transferred words, and table end code [phase] of the data block ■.

In this link array chain mode, tables X are linked from ■ to ■ by link addresses, and table Y is linked from [phase] to O by link addresses, so processor 5 uses The start address of table X is set, and the start address of table Y is set in table address register 19, but block count registers 20 and 2
1 does not allow the number of data blocks to be set.

Here, the processor 5 instructs the main control unit 10 to start up. The main control unit 10 that has been instructed to start uses the table X stored in the table address register 18 via the bus control unit 11.
The first address of the table Y stored in the table address register 19 is read via the bus control unit 22.

The main control unit 10 reads the contents of tables X and Y in the memory 2 using the start addresses of tables X and Y, and stores the memory address @ and link address ■ in the address register 12.
The number of transferred words 0 is stored in the word count register 14, the device address [phase] and the link address [phase] are stored in the address register 13, and the number of transferred words [phase] is stored in the word count register 15.

When the main control unit 10 transfers a data block from the memory 2 to the input/output device 4, it successively sends the data block ■ at the address specified by the memory address ■, and the device address [phase] of the input/output device 4 passes through the lotus 24. Store in the specified buffer memory area ■.

Here, if the number of transferred words ■ and [phase] are the same, the data block ■ is entirely transferred to the area indicated by the data block ■.

Next, the main control unit 10 stores the memory address [phase] and the link address ■ in the address register 12 from the table X using the link address ■, stores the number of transferred words ■ in the word count register 14, and stores the link address [phase] The device address [phase] and the link address [phase] are stored in the address register 13 from table Y using , and the number of transferred words [phase] is stored in the word count register 15 using .

Then, the data block ■ is successively generated at the address specified by the memory address ■, and the buffer memory area ■ specified by the device address [phase] of the input/output device 4 is sent via the bus 24.
Store in. Here, if the number of transferred words @ and 0 are the same,
Data block ■ is entirely transferred to the area indicated by data block ■.

Next, the main control unit IO uses the link address ■ to input the memory address [phase] from the table X into the address register 12.
Store the link address [phase] and the number of transferred words [phase] in the word count register 14, and store the device address [phase] and table end code [phase] in the address register 13 using the link address O. The number of transferred words [phase] is stored in 15.

Then, the data block (2) is successively generated at the address specified by the memory address @ and stored in the buffer memory area (2) specified by the device address O of the input/output device 4 via the bus 24. Here, since the number of transferred words [phase] is less than [phase], data block ■ is entirely transferred to the area of data block ■, but the main control unit 10
From the difference, the starting address in the buffer memory area (■) for storing the next data block is recognized.

Then, the main control unit IO uses the link address @ to transfer the memory address 0 from the table X to the address register 12.
and the table end code O, and the number of transferred words O are stored in the word count register 14, and the data block ■ is successively generated at the address specified by the memory address ■, and is stored in the buffer memory area ■ of the input/output device 4 via the bus 24. .

Here, if the number of transferred words [phase] and the number of transferred words [phase] 10 are the same, data blocks ■ and ■ are all transferred to the area indicated by data block ■.

The main control unit 10 recognizes that the data block transfer is completed based on the table end code stored in the address registers 12 and 13.

When the main control unit 10 transfers a data block from the input/output device 4 to the memory 2, it is the same as described above, and since it can be easily inferred, a detailed explanation will be omitted.

〔Effect of the invention〕

As explained above, according to the present invention, the processor 5 only needs to activate the DMA control circuit 6 once, and there is no need to intervene after that, reducing the burden on the processor 5, thereby increasing the processing efficiency of the system. I can do it.

FIG. 5 is a diagram illustrating the operation of FIG. 4.

In the figure, 1.5 is the processor, 2 is the memory, and 3.6 is the DM.
A control circuit, 4 an input/output device, 7 an instruction means,
8 is a storage means, 9 is a control means, 10 is a main control section, 11.22 is a bus control section, 12.13 is an address register, 14, 15 are word count registers, 16, 17 are channel control registers, 18, 19 is the table address register, 20.21 is the block count register, 23 is the program,
24 is a bus.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention. FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention; Fig. 3 is a diagram explaining the operation of Fig. 2; Figure 4 is a block diagram illustrating the conventional technology. ) The city of Tsukasa and 2nd ward will be closed on August 1st. Book 3 Diagram C-A 1)

Claims (1)

[Claims] A processor (5), a memory (2) that stores instructions and data used by the processor (5), and the memory (2)
an input/output device (4) that performs data transfer, and a direct storage access control that controls data transfer between the memory (2) and the input/output device (4) based on information set by the processor (5). In a system comprising a circuit (6), the direct memory access control circuit (6) includes the input/output device (
4) and a storage means (8) for storing information for mutually transferring a plurality of data blocks between the memory (2), and the input/output device based on the information stored in the storage means (8). (4) and a control means (9) for controlling the transfer of a plurality of data blocks between the memory (2), and the processor (5) is provided with a control means (9) for controlling the transfer of a plurality of data blocks between the memory (2), The storage means (8) is provided with instruction means (7) for instructing to store information for mutually transferring a plurality of data blocks between the input/output device (4) and the memory (2), and the processor (5) is the direct storage access control circuit (6
), the information instructed by the instruction means (7) is stored in the storage means (8) of the direct storage access control circuit (6).
), data between the input/output device (4) and the memory (2) is controlled by the direct storage access control circuit (6) without the processor (5) intervening again. A direct storage access control method characterized by completing a transfer.