JPS5856056A - Interchange processing system - Google Patents

Abstract

PURPOSE:To increase an arithmetic processing speed by writing interchanged data twice successively when a data interchange instruction is outputted. CONSTITUTION:When a data interchange instruction is outputted, the output NA1 of an NAND circuit 19 goes down to 0 at timing t3 to close a gate G4. At this time, the output FF1 of an FF3 is held in a state 1 and a gate G4 is still open. Therefore, contents for an Y register which is outputted from an RAM10 and held in a buffer 12 are sent through an adder circuit 13 to the RAM 10, and written in an X register. When the output NA1 goes down to 0, on the other hand, 0 is written in the FF3. When the output NA1 is 0, the output of an NAND circuit 18 goes up to 1, which is written in an FF4. Therefore, the timing signal t3 is held at the level 1 successively even one digit later. Then, when the output FF1 goes down to 0, the output NA1 goes up to 1 and the gate G3 is opened to close the gate G4. Therefore, the data of the X register of the a buffer 11 is inputted to the RAM10.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an exchange processing method for exchanging data in a computer 417 in a small electronic calculator.

For example, in a conventional small electronic computer using the ROM-RAM system, each digital,
The tie ζ solder signals t1 to 1 . by 3
The data is divided, data is read at a timing of tl*tl, and data is written at a timing of ts. Therefore, when data is exchanged between different registers configured in RAM, 1 digital data is used.

It requires 2 digital and 5 timings for data exchange. In this case, the second digit is a turtle that only performs writing processing using 1.0 timing! +, tl*t
Timing l is not used and is wasted time.

The present invention has been made in view of the above points, and one object thereof is to provide an exchange processing method that eliminates wasted time when exchanging data, shortens calculation time, and waits.

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, reference numeral 1 denotes a pulse generator which generates the reference pulses φ1 and φ shown in FIG. The above-mentioned signals φl and φl are sent to the control section 1 and inputted to delayed flip-flops 3, 4 and 5 as input read/read signals. In addition, the above-mentioned analogy φ1 is input to the NASHID circuit 6 and also to the AND circuit r*8-1. However, the control section 1
A RAM (RAM access memory) IO that stores various microfa dams and outputs them from the output line.
Column address magazine for output 2 in b to RAM I
The line that defines the X register in O is at7 X 8u *
Output 2 input is the row address Fu that specifies the X register in RAM I O, output line d is the data exchange instruction Ex1, output line WRITIC condition signal,
A subtraction instruction SB is output from the output fin f. The column address LA output from the control section 2 is
10 column address terminals I and AK are input, and the row address Su"u is inputted to the RAM JOO row address terminal UA via r-to@W&Gs-G, respectively. This RAM 10 KB, the above-mentioned X register In addition to the and
It is input to J1. The input terminal 11 reads the input at the timing tl·φ1, and inputs data to the input terminal 11 at the timing φ3. Also, I4 Tuffa 1
2 reads the input at the timing of kl -φ and outputs the data at the timing of φ1, r-) circuit G4
is input to the input terminal B of the candy circuit 1s via the candy circuit 1s.This candy circuit 11 normally performs an addition operation, and the control unit 1
A subtraction operation is performed when a subtraction command 8B is given from .

The calculation result is input to the input terminal IN of RAM JO. Therefore, the outputs of the above-mentioned trees, guts a, , y' 5 are the timing signals 1. and υ are input to the AND circuit 1 and r of the dirt circuit G through the NOR circuit 14.
–) is input to the terminal. Furthermore, the output of this NOR circuit 14 is inputted via an inverter 15 to the r-) terminal of the r-) circuit GK. Then, the output of the AND circuit 1 becomes a tie (nr (l t s−φ!), and the output from the AND circuit 1 becomes
is input to. ti, the output of the flip-flop 5 is outputted as a timing signal t1 through the NOR circuit J- along with the output of the free-lag flop and 'f4, and is input to the AND circuit 11 and the NAND circuit 18.
The output of the AND circuit 9 is input to the timing signal 1.・It becomes φ1 and is input to /4 tsfa I]. Then, the outputs of the above-mentioned FRI, f-Flo, and f4 are timing signal color 3 υ.

In addition to the NOR circuit 16 described above, the signal is input to the NAND circuit 6.degree. 19, and is inputted to the FRI, PUFRO, and D5 together with the arm via the AND circuit 20. The WRITI condition signal is input to the NAND circuit C from the control unit 2, and its output is read/output.
The write command RAW is input to the RAM 10.

In this case, a read command is issued when the output of the NAND circuit 6 is @1#.

“Om” becomes a write command. Also, the AND circuit 20
The output is input to the AND circuit 8, and the output is sent to the control section 1 as column address count-up signals φ and C. Then, the data exchange command Ex is inputted from the control section 2 to the first command circuit 19, and the r-) circuit G@Q? '-) terminal, and is also input to the AND circuit 20, the NAND circuit 18, and the flip-flop 1. Then, in addition to the output of this ant, f-flow, and de-3, in addition to the above-mentioned NAND circuit 1#, it is input to the dirt terminal of the dirt circuit G4, and is also input to the NOR circuit 1 via the inverter 21.
4. t, above yellowtail, defrodeg5. The timing signal ttt1e%1 outputted from the NOR circuit 7g, the free lag flow, and the f a th is sent to the control section 2.Next, regarding the operation of the above embodiment, the second @ tie power? Explain with reference to the chart. During normal operation when the data exchange command Ex is not output, the machine cycle T1 has the same time width as shown in FIG.
t #t. That is, when the data exchange command Ex is @01, the output NA of the NAND circuit J9
J is always 11 degrees, so the output of the flip-flop S is held at 4''1''. Then, when the tie voltage signal tl is output in the machine cycle at the branch of Tl, the output of the AND circuit 20 When A3 becomes "1", it is read into the free νdefro and pu5 in synchronization with the mother pulse φl. The 9'''' 1m signal read into the FRI, DEFLO, G5 is output in synchronization with the BLACK, RI, DALSU φ■, and the TIE signal t in the machine cycle T1.
It becomes 1. This tie signal t1 is outputted until the next black and cold pulses φ snow are applied. When the tie setting signal t1 becomes 101, the NOR circuit 16 outputs the °11 signal, and the tying signal 1. becomes.

When this timing signal ts is output, the inverter IT
The output of is "0", the output NAJ of NAND circuit 18 is @1m
Then, in synchronization with the clock pulse φ1, the differential opening,! 4 and is output in synchronization with the clock I mother pulse φ reference. The output of this flip 70 output 4 becomes the tie conductor signal is.

When this timing signal ts is output, the output of the NOR circuit 16, the output of the υ tie conductor signal 1. becomes "O", and the tie conductor signals t1-1. are output sequentially. Therefore, when the tie signal t1 is output, the output of the NOR circuit 14 becomes @0 and the output of the #1 inverter 15 becomes 111, r-) of the circuit G1 is opened, and the output from the control unit 1 is The output row address S is sent to RAM JO. By this row address Stl, RAM r
The Yv register in o is specified. 1 Also, when RAM
10 is given the column address XLA from the control unit 2, and Y
A column address of a register is specified and its contents are read. Further, when the timing signal t1 is being output, the AND circuit r outputs a timing signal t1.phi.1 synchronized with the clock signal φ1, and is sent to the gate 1 and the NOR 12. Therefore, the data read from RAM 10 is
It is read into the shipper 11 by the timing signal tl·φ1.

When the timing signal t1 is output, the AND circuit 9 synchronizes with the timing signal 1.・φ1 is output and Pa.

Sent to 7yl. At this time, the timing signal t1 is @
O'', the output of the S NOR circuit 14 becomes @1'', and r-
) circuit Gseng r−) is opened. Therefore, the row address xF output from the control unit 2 is sent to the RAM 10, and x v
y x is specified. In addition, since the column address LA is sent from the control unit 1 to the RAM J o, the contents of the The data held in the 7-inch shaft 11.11 is sent to the American circuit IS via the dart circuit G1eG4.

Then, timing signal 1. is output, WRIT
According to the E condition, from the NAND circuit 6 a, 1 coulus φ
``0''0'' signals are sent in synchronization with Otori.

This @01 number is sent to the RAM 10 as a write signal. At this time, RAM JO has a tie of 1 (as at 71, the row address r and column address for the KXL/register are given, so the operation result of the candy circuit IJ is written to the XV register. % In the case of the tSO tie conductor KTh, the output AJ of the AND circuit 10 is 111, so the AND circuit 8 outputs the counter f signal φ2. in synchronization with the analogy φl, and the control unit 1
When the control unit 2 receives the counter and f signals φ and C, it increments the column address LA by "+1" and designates the next column address. Thereafter, arithmetic processing is performed for each column of the XV register and Yv register in the same manner.

Next, the operation when performing data exchange processing will be explained. When exchanging data.

The data exchange command 118x is output from the control section 1, and the machine cycle T 9 writes 2 digits worth of data to the RAM JO by doubling the time width of the tying signal ts. One digital and one digital data are written to the x and Y registers respectively.In other words, when the data exchange command Ex is output, until the tl tie is reached, the Since the signal input from 4 to NAND circuit J9 is 1'am, the outputs of FRI, DEFR, and DES are held in @1m shape 1[K in the output NA7 of NAND circuit 1#.Therefore, tl, tl
The timing signal is the same as in the normal calculation above,
The contents of the X register and Y register 12 of RAM JO are respectively read into the DV sofa 1°12. and,
ts tie (when it enters NANDa, it becomes a NAND circuit! Output NAJ of #
is 10 m, p-) of the AND circuit 20 is closed, and r-) circuit G50r-) is closed.

At this time, the output FFM of the defroster f3 is held in the 11m state, and the r-) of the F"-) circuit G4 is opened. Therefore, the contents for the Y register held in the F"-) circuit G4 are stored in the adder circuit. RAM J via IS
O and written to the X register specified by row address F and column address LA. As described above, the output NAJ of the NAND circuit 19 becomes @0''', the flip-flop, and the 7'jK clock I analog pulse φ.

@Om is read by φ■. In addition, when the output of the NAND circuit 19 is @O", the output of the NAND circuit IJ is 11m. Therefore, the timing signal 4m continues to be held at the 1" signal level even after the completion of the 1st digit. Therefore, the timing of ts enters the 2nd digit, and as described above, the output F of the floating flag fJ
When FM reaches 10#, the f-) of the r-to circuit G4 is closed and the output of the impurator 21 becomes @11 and the NOR circuit 14.
The output of the input terminal 15 becomes @0'' and the dart of the r-) circuit G3 is closed. At the same time, the output of the in/output 15 becomes ``1'' and the ff-) of the r-) circuit G1 is opened. The row address s1 outputted from is sent to the RAM 10 and the Y register is designated.On the other hand, when the output FFM of the above tree, shift0.g8 becomes @Om.

The output NAJ of the NAND circuit 19 returns to @1# again, and the gate of the AND circuit 20 is opened and the gate circuit G s O
Therefore, the data for the X register held in the P/F 11 is transferred via the American circuit
AM JO is input.

Then, at the second digital of this ts timing, a write command is output from the 4 NAND circuit 6 in synchronization with the black and red pulses φ1, so the above-mentioned American circuit 13 outputs the RA
The data sent to M 1 o is written to the Y register. Also, as mentioned above, the AND circuit 20(1)? '−
) is opened, its output becomes "1" and is input to the AND circuit 8, and the count up signal φ1c is output from the AND circuit 8 in synchronization with the clock pulse φ1. When the output NAJ of the circuit 19 returns to "1", the output of the NAND circuit 18 is read in synchronization with @Om and the clock pulse φIK.

Then, the timing of ts ends when the 10- signal read into the O-free, defro, and de-4 is outputted in synchronization with the black and cool arms φ. At the same time, the outputs of the AND circuit 20 are read into the frits flow and goo in synchronization with the outputs of the AND circuit 20, RI, and φl, and a timing signal t1 is generated to enter the next machine cycle. Thereafter, data is exchanged in each column of the X register and Yv register in a similar manner.

It should be noted that the present invention is not limited to the above-mentioned embodiment, and it goes without saying that it can be implemented using other circuit configurations.

As described above, according to the present invention, when a data exchange command is output, the machine cycle is extended by 1/3 digital, and write processing is performed continuously. exchange can be carried out efficiently,
Arithmetic processing speed can be improved. That is, when exchanging data of one digit, conventionally two digits were required, but in the present application, one digit is required.

) + 1/3. Therefore, for example, when converting data of 8 digits, the conventional method requires 16 digits and 0 processing time, whereas the present invention requires 10 digits
) + Finishes in 2/3, reducing processing time to 2/3.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention; FIG. 1 is a circuit configuration diagram, and FIG. 2 is a diagram for explaining the operation. l... Lux generator, 2... Control unit, 3.4.8
...Furi, fF4, De, 10...RAM (?Random Access Memory), G4-G4...r-) Circuit/Applicant's agent Patent attorney Takehiko Suzue JP-A-1983
-56056 (5)

Claims (1)

[Claims] In a processing device that reads data stored in a memory and performs arithmetic processing, when an instruction is issued to exchange data stored in different storage areas of the memory, the machine cycle for data exchange is extended and An exchange processing method characterized in that writing operations of exchange data to different storage areas are performed twice in succession.