JPS62146064A - Multi-port memory - Google Patents

Abstract

PURPOSE:To miniaturize a system by performing the write operation of a serial data to the first and the second write line buffers, and the read operation of the serial data from previous stated first and second read line buffers asynchronously with each other and in parallel. CONSTITUTION:RDYs 1, 2, 3, and 4 are constituted so that each of them has a function to inform transfer operations to open a data write transfer gate 1, a data read transfer gate 1, a data write transfer gate 2, and a data read transfer gate 2 to an outside, and decides a priority and performs it in order when plural transfer operations are executed simultaneously based on each of the RDY signals with an external control. Thus, except when a data transfer period is made extend in a form to wait, each operation at total four ports, two each for a serial write and a serial read, can be performed independently with each other and asynchronously.

Description

[Detailed Description of the Invention] [Technical Field to which the Invention Pertains] The present invention relates to semiconductor memory assemblies and circuits, and in particular to configurations that are effective in transmission-based image processing systems. Demand for semiconductor memory in transmission-based image processing systems such as printers and printers is increasing significantly.

This will be explained below using the drawings. The configuration of such a system can generally be manipulated as shown in FIG. Transmission input data is stored in a memory, and the CPU modifies the data contents via the controller to create transmission output data. The memory needs to be able to receive and receive data for transmission purposes as well as receive access from the CPU. Since a large capacity is usually required, if a standard MOS dynamic RAM is used, the memory must be provided with peripheral circuits shown within the dotted line frame, as shown in FIG. An example of the image of transmission data in this system is as shown in FIG. The transmission input data enters the memory sequentially from the first row to the Mth row from left to right in pixel units of 1M rows and XN columns. In order to match the data cycle time, the converted data is placed in a register and written to multiple R and AM simultaneously. The CPU modifies the data thus entered, and for example, in the case of FIG. 3, the data in the frame is added to the upper part of the screen. Exactly the opposite of the corrected single input, data from a plurality of inputs is transferred to a register all at once and subjected to parallel-to-serial conversion to become output data. At this time as well, the first to Mth rows are read from the left to the right of the screen. Writing and reading of transmission data are completely serial operations, and data modification by the CPU can basically be performed serially row by row. At present, it can be said that it is extremely wasteful to use a RAM that can be randomly accessed and to add serial address input to the periphery. That is, there is no memory that can accommodate the required address movement, and the current MOS dynamic RAM cannot keep up with the data cycle time, which are obstacles to miniaturizing the system and improving operating efficiency.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory that realizes the functions of the memory in the transmission-based image processing system shown in FIG. 1 without the need for peripheral circuits or external address generation circuits shown in FIG. 2 that speed up the data cycle time.

[Structure of the invention]

According to the present invention, memory cells are arranged in m rows and n columns, a decoder receives an external count clock input and selects one of the m rows of memory cells, and n bits store data serially written from the outside. 1) a first data write transfer gate that transfers and convolves the data of the first write line buffer having a width of a first read line buffer with a width of n bits that stores the data of one row of memory cells and serially outputs it to the outside; and a first read line buffer that stores data of the n bits of memory cells selected by the decoder; A first data read transfer gate that transfers data all at once to a buffer, a serial decoder that receives an external clock input and repeats row selection from the 1st row to the mth row, and an n-bit data that stores data written serially from the outside. a second data write transfer gate that transfers and stores data in the second write line buffer to an n-bit memory cell selected by the serial decoder; a second readout 2-in buffer with a width of n bits that stores the data of the memory cells for a row and serially outputs it to the outside; and a second readout line buffer that stores the data of the n-bit memory cells selected by the serial decoder; of the first and second data write transfer gates and the first and second data read transfer gates so as not to temporally overlap with each other. Serial data write operations to the first and second read line buffers, and the first and second read line buffers, except for line buffers related thereto during a data transfer operation period in which one is open; A multi-board semiconductor memory is obtained which is characterized in that a total of four serial operations, including serial data read operations from A to A, are performed asynchronously and in parallel.

[Explanation of Examples]

FIG. 4 shows the basic configuration of the multi-board memory of the present invention. To explain the order of data flow, first, transmission input data enters the write line buffer 2 from the serial data input 2 in synchronization with the write clock φW2. When up to n bits are serially input, this line buffer is no longer full, and the data write transfer lock WDT2 is activated and the contents of the line buffer are specified by the serial counter l and row decoder 2 through the data write transfer gate 2. write to the first row of memory cells that have been written. When this data transfer operation is completed, the contents of serial counter l will be +
1 (increment) to prepare for the next transfer operation and allow data to be continuously sent to the serial data input 2. When n bits are entered again, WDT2 is activated and the contents of write line buffer 2 are transferred to the second row of memory cells. This operation is repeated until the first row to the mth row are filled with data, and then the first row is replaced with new data. Modifying data entered into a memory cell can be done as follows. Modifications may be done within the same row, or may include data from other rows. In any case, the row containing the modified data can be specified by activating the count clock input a necessary number of times. By activating the data read transfer lock RDTl, the row is selected by the address counter and row decoder l, and the data of the memory cell is transferred to the read line buffer 1 through the data read transfer gate l. Even after the transfer, the data in that row will be stored as it was. By activating the read clock φ3 n times, the read line buffer 1
The contents are serially output to serial data output 1.

It is necessary to prepare a logic circuit that externally generates data to be given to the row to be modified based on this data. The result is sent from serial data input 1 to write clock φ1.
, and is sent to write line buffer 1 in synchronization with . After activating the count clock input the necessary number of times to specify the row to be modified, activating the data write transfer lock WDTI causes the memory cells in that row to be selected by the address counter and row decoder l. The contents of the write line buffer 1 are stored through the data write transfer gate 1.

In this way, (1) memory cell in the row containing modified data → (
Correction work is performed on the transmission input data in the following order: 2) read line buffer 1→(3) correction data creation→(4) sorting line buffer 1→(5) memory cell of the row to be corrected. By activating the data read transfer lock RDT2 on the premise that data modification has been completed, the serial counter 2 and row decoder 2 sequentially select the first to mth rows, and the The data of each row is transferred to the read line buffer 2, and this process is repeated. Transmission output data is obtained at the serial data output 2 by activating the read clock φ1□ n times each time data is transferred to the read line buffer 2 by activation of RDTz.

Terminal functions necessary to embody the memory having the configuration shown in FIG. 4 are shown in FIG. count clock input,
Serial data inputs 1-4 and serial data output 1
~4 respectively C0UNT, 5D11~4 and 5DO
0RESET represented by t~4 sets all the contents of the address counter, serial counter 1, and serial counter 2 to 0. That is, it plays the role of bringing the first row of memory cells into a state of selection, and is activated at intervals of a unit amount of data. RDYI, 2.3 and 4 are data write transfer gates 1.3 and 4 respectively. Data read transfer gate 1. It has a function to notify the outside of the transfer operation when the data write transfer gate 2 and the data read transfer gate 2 open, and when multiple transfer operations occur at the same time, they are prioritized and performed in order based on each DY signal using external control. I'm trying to do that. Except for the fact that the data transfer period may be delayed and lengthened in this manner, the operations of each of the four ports, two for each serial write and serial read, can be performed independently and asynchronously.

This is because the line buffer and memory cell are disconnected during periods other than the data period when the transfer gate is open, and data exchange between the data output and the line buffer is interrupted.

〔Effect of the invention〕

According to the present invention, it is possible to obtain a multi-board memory having the function of receiving transmission input data, correcting it based on accumulated data under CPU control, and outputting the result as transmission output data, and these operations can be performed independently and asynchronously. Therefore, system operating efficiency can be significantly improved, and by incorporating the peripheral logic surrounded by the broken line shown in Figure 7 and limiting it to serial operation on a line-by-line basis in accordance with the actual system, as shown in Figure 5. As shown in Figure 2, since there is no need for an address terminal and the number of pins is small, the system can be made more compact, making it very effective as a memory for transmission-based image processing systems.

[Brief explanation of drawings]

Figure 1 shows the configuration of the image processing system for the transmission system.
The figure shows the configuration of the same system using a conventional standard MOS dynamic RAM, Figure 3 shows an example of the movement of transmitted data and one modification, and Figure 4 shows the basic configuration of a multi-board memory according to the present invention. , FIG. 5 shows the terminal functions necessary to implement this memory.
, 2-1 Agent Patent Attorney Susumu Uchihara (,-
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Claims (1)

[Claims] Memory cells arranged in m rows and n columns, a decoder that receives an external count clock input and selects one of the m rows of memory cells, and a decoder with a width of n bits that stores data serially written from the outside. 1 write line buffer, a first data write transfer gate that transfers and writes data in the first write line buffer to n-bit memory cells selected by the decoder, and a first data write transfer gate that transfers and writes data in the first write line buffer to n-bit memory cells selected by the decoder; a first read line buffer with a width of n bits for storing and serially outputting to the outside; and a first data read that transfers data of n bits of memory cells selected by the decoder to the first read line buffer all at once. a transfer gate, a serial decoder that receives an external clock input and repeats row selection from the first row to the mth row, and a second write line buffer with a width of n bits that stores data serially written from the outside. a second data write transfer gate that transfers and writes data in the second write line buffer to n-bit memory cells selected by the serial decoder; and a second data write transfer gate that stores data in one row of memory cells and serially outputs it to the outside. a second read line buffer with a width of n bits, and a second data read transfer gate that simultaneously transfers data of n bits of memory cells selected by the serial decoder to the second read line buffer; A line buffer related to the first and second data write transfer gates and the first and second data read transfer gates during a data transfer operation period in which any one of the first and second data read transfer gates is opened so as not to overlap with each other in time. except that a total of four serial operations, ie, a serial data write operation to the first and second write line buffers and a serial data read operation from the first and second read line buffers, are performed asynchronously and in parallel with each other. A multi-port semiconductor memory characterized by: