JPS62236195A - Memory device - Google Patents

Abstract

PURPOSE:To improve a speed inputting and outputting data and to simultaneously attain I/O actions by constituting such that parallel data of one word is written and read in a memory part. CONSTITUTION:The title device is provided with an input control part 12 that converts input data made of serial data into parallel data of one word and transmits it as write data, a memory part 13 with a memory cell matrix structure that stores write data as parallel data of one word and an output control part 14 that reads data in the memory part 13 is parallel data of one word. For writing data, the input control part 12 converts data inputted in a format of serial data input parallel data of one word and stores it in the memory part 3. At the time of reading data out of the memory part 13, the output control part 14 reads that in the memory part 13 as parallel data of one word. Thus the memory device 11 improves its I/O speeds, and attains I/O actions simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to memory devices, such as RAM (ran
It is suitable for application to memory devices such as dom access 5esory) and shift registers.

B. Summary of the Invention The present invention provides a memory device in which a storage section is
By configuring the device to write and read parallel data, it is possible to improve the data input/output speed and perform input/output operations simultaneously.

C. Prior Art Conventionally, a memory device consisting of this type of RAMI, for example,
As shown in the figure, a storage section 5 having a memory cell matrix configuration
, an X address designation section 3, an X address designation section 2, and a write/read circuit 4.

The storage section 5 has a structure in which memory cells made of flip-flop circuits are arranged in a matrix. Address specification section 2
．． 3 applies an address selection pulse to the word line and column line of the storage section 5 based on address data ADH given from the outside, selects the memory cell at the specified address, and specifies 1 bit of data as the X address. Writing or reading is performed via the section 2 and further via the write/read circuit 4.

The storage unit 5 is controlled to read or write data by a read/write signal R/W given from a CPU (not shown).

In the configuration shown in FIG. 2, by writing data from the CPU through the input/output line 0 and reading the data after a predetermined period of time, it is possible to form shifted data as necessary.

Problems to be Solved by the Invention However, in this conventional RAMI, data is input and output using a common input/output line IO. Cannot be done at the same time.

In addition, the configuration shown in FIG. 2 has a long signal path from the input/output terminal to the storage unit 5, and
Since it is necessary for the address specifying section 2 and the Y address specifying section 3 to perform address selection processing and processing to write or read data to the memory cell at the address, it is necessary to
I have the disadvantage that the overall operating speed is slow.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a memory device that can simultaneously perform data writing and data output and has a high operating speed.

E Means for Solving the Problem In order to solve this problem, the present invention includes an input control section 12 that converts input data consisting of serial data into one word of parallel data and sends it as write data.
and a storage unit 13 having a memory cell matrix configuration that stores the write data as 1 to 1 minute parallel data;
The apparatus further includes an output control section 14 that reads out the data in the storage section 13 as the one word worth of parallel data.

When writing F action data, input data input in the form of serial data is converted by the input control section 12 into one word of parallel data and written into the storage section 13 .

Further, when reading data from the storage section 13, the output control section 14 reads out the data from the storage section 13 as one word of parallel data.

Thus, the memory device 11 has improved input/output speed and can perform input/output operations simultaneously.

Embodiment G An embodiment in which the present invention is applied to a RAM will be described in detail below with reference to the drawings.

In FIG. 1, 11 indicates a RAM as a whole, which is composed of an input control section 12, a storage section 13, an output control section 14, and an address setting section 15, and these components are formed on the same semiconductor chip. .

The input control unit 12 inputs input data D4 consisting of serial data arriving one bit at a time through the input line IN to a serial/parallel conversion circuit 16 having a shift register configuration from the upper bit side, and the serial/parallel conversion circuit 16 converts the input data D4 to lθ. The converted parallel data Bl is once latched into the latch circuit 17 and then written into the storage section 13 by the write circuit 18.

The storage unit 13 has 10
In order to write and read data in units of 10-bit memory cell rows (the amount of data stored in 10-bit memory cells is called one word) by arranging 10-bit memory cells, i.e. column line direction)
for a predetermined number of words (in this example, 1827 words)
memory cell columns are arranged.

The output control unit 14 reads out one word worth of data stored in the memory cell column to which the word address specified by the address designation unit 15 has been assigned, all at once by the continuous output circuit 19, in response to a read command from the CPU separately. The data D is input to the parallel/serial conversion circuit 20 having a shift register configuration, and is converted into serial data, and output data D from the lower bit side to the output line OUT. U? I close it and send it out.

The addressing section 15 selects a word line in the storage section 13 based on address data ADR given from the outside by the address decoder 22, and also selects a word line of the storage section 13 based on the address data ADR given from the outside by the address decoder 22.
The operation timing of each part is determined based on the following.

In this embodiment, the input control section 12, storage section 13, and output control section 14 are controlled by the timing generator 21 and address decoder 22 of the address specification section 15,
Each part operates in a so-called pipeline control manner. This allows data to be input and output to and from the storage unit 13 asynchronously.

In the above configuration, when writing data to RAM II, the data DIN that arrives one bit for each clock via the input line IN is input from the upper bit side of the serial/parallel conversion circuit 16 and is written one bit at a time to the lower bit. The data is shifted to the bit side, serial/parallel converted every 10 clocks, and sent to the latch circuit 17 as parallel bit data B1.

The latch circuit 17 temporarily holds this parallel bit data Bl, and when the latch pulse signal S1 is obtained from the timing generator 21, the parallel bit data B2 is transferred to the write circuit 1.
Output to 8.

The write circuit 18 writes the parallel bit data B3 to the designated address of the storage unit 13 in accordance with the write signal S2 sent from the timing generator 21 when the word line of the storage unit 13 is stably selected by the address decoder 22. Write to memory cell.

Also, when reading data, address decoder 2
2, when the word line of the storage unit 13 is stably selected, the readout circuit 19 reads out the stored data B4 of the memory cell column connected to the word line at once and reads l words. It is sent to the parallel/serial conversion circuit 20 as parallel bit data B5.

At this time, the parallel/serial conversion circuit 20 starts parallel/serial conversion by the parallel/serial conversion pulse S3 given by the timing generator 21, and converts the serial bit string from the least significant bit of the parallel bit data B5 by 1 bit every l clock. Output data I
), at are output to the output line OUT.

According to the above configuration, the data processing executed inside the RAM 11 in order to write or read the input data DIN to the storage section 13 is executed at once for each 10-bit parallel data. Therefore, as in the conventional case, 1
The operating speed can be increased approximately 10 times compared to when writing or reading is performed bit by bit.

In general, in this type of memory device, the time required to write and read data to and from the memory cell matrix after waiting for the word lines and bit lines of the memory cell matrix to be in a stable selected state is longer than conventional methods. This is because, in contrast to the case where the processing is required every time one bit of data is processed, according to the above-described embodiment, it is necessary to process the parallel data of 10 bits once. In this way, a high-speed RAM can be easily realized.

Furthermore, since the data flow of the RAM II is pipelined, from an external perspective, simultaneous write and read operations can be performed.

In the above-described embodiment, an example was described in which parallel processing is performed using 10 bits as one word, but the number of bits in an l word is not limited to this and can be selected to be any number. In principle, the larger the number of bits in an l word, the faster the input/output speed can be.

Further, in the above-described embodiment, only one stage of latch circuit 17 is provided for write timing control, but a plurality of stages may be provided. Furthermore, one or more stages of ladder circuits may be provided between the successive output circuit 19 and the parallel/serial conversion circuit 20 in order to control the read timing.

Furthermore, in the embodiment described above, the addressing section 22
Although the memory is configured to be provided internally, it may be configured to receive addressing data from an address specifying section provided in common with other memories connected to the data bus.

Further, in the embodiments described above, an example was shown in which the present invention was applied to a RAM, but the present invention is not limited to this, and the present invention can be widely applied to memory devices such as shift registers.

Effects of the Invention As described above, according to the present invention, it is possible to easily realize a memory device that can simultaneously perform input and output operations at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment in which a memory device according to the present invention is applied to a RAM, and FIG. 2 is a block diagram showing a conventional example. 11...RAM, 12...Input control unit, 13...Storage unit, 14...Output control unit, 15...Address specification Department.

Claims (2)

[Claims] (1) An input control unit that converts input data consisting of serial data into one word of parallel data and sends it as write data, and a memory cell matrix configuration that stores the write data as one word of parallel data. A memory device comprising: a storage section; and an output control section that reads out data in the storage section as parallel data for one word. (2) The memory device according to claim 1, wherein the input control section, the storage section, and the output control section are configured on the same chip.