JPS63241785A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce load on a CPU and to accelerate processing speed, by performing data transfer on a path where data is transferred from a memory cell array to a transfer register and to the memory cell array in a transfer mode. CONSTITUTION:When the data transfer is performed in the inside of a main memory without inputerosing the CPU, a transfer mode instruction input from the CPU becomes active for a constant time in a first RAS cycle I. At this time, the content of the memory cell array 1 at an address designated by an address input is read out, and is transferred to a transfer register 12 via a multiplexer 13. Next, in a second RAS cycle II, the signal input of the inverse of WE from the CPU becomes active for the constant time, and a transfer mode designation capacity becomes active. At this time, the content of the memory cell array 1 at the address designated by the address input is transferred via the multiplexer 13. By repeating such operation corresponding to the data transfer, it is possible to perform the data transfer between the memories without interposing the CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory, and particularly relates to a semiconductor memory having a data transfer function between memory cells.

(Prior Art) In a total of X machines, for example, as shown in FIG. Conventionally, the process of embedding (transferring) t character strings starting from the m-th character of character variable A into t character strings starting from the n-th character of number B is performed as follows. First.

Each byte address of the mth character of character variable A (3rd character in this example) and the nth character (2nd character in this example) of character variable B (in this example, 1 character is physically assigned to 1 byte) ”) BAA, B
AB is required. Next, character data of tlm (31tIA in this example) starting from address BAA of the main memory is transferred to three character data starting from address BAB. At this time, data is transferred for each character data through a route from main memory to CPU (medium heat processing unit) to main memory.

However, the reason why the CPU has to intervene in the data transfer path is that there is a difference in processing speed between the main memory and the CPU, so the processing speed of the CPU decreases due to the burden associated with the data transfer. There is a problem. The reason why the CPU's intervention is required is that the conventional semiconductor memory used as the main memory is not configured to handle data transfer between memory cells by itself.

(Problems to be Solved by the Invention) The present invention was made in order to solve the above-mentioned problem that the load on the CPU increases when data is transferred within the main memory. An object of the present invention is to provide a semiconductor memory that can reduce the burden on a CPU when transferring data in the main memory when used as the main memory of a computer.

[Structure of the Invention] (Means for Solving the Problems) The semiconductor memory of the present invention includes means for writing data from the outside into a memory cell array, means for reading data from the memory cell array to the outside, and a transfer mode instruction input. A transfer register that stores data extracted from the memory cell array during an instructed transfer mode and holds it for at least two memory cycles; The method is characterized by comprising means for writing into the memory cell array.

(Function) In addition to normal read/write operations, in the transfer mode, data can be transferred along the path from memory cell array to transfer register memory cell array. Therefore, when used as the main memory of a computer, the memory itself can transfer data between memory cells within the main memory, and the CP
The burden on U becomes lighter and its processing speed increases.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a part of a semiconductor memory, in which 1 is a memory cell array, 21 to 2n are row address input terminals, 3 is a row address buffer, and 4 is a memory cell array that decodes the word line of the memory cell array 1. row decoder to select,
51 to 5mf"i column address input terminal; 6 is a column address buffer; 7 is a column decoder for decoding a column address to select a column of the memory cell array 1; &l"i data input terminal; 9 is a data output terminal; 10 1 is a human output buffer 7 for inputting and outputting data between the data input terminal 8 and data output terminal 9, 1 is a transfer instruction input terminal to which a transfer mode instruction signal is input from the outside, and 12 is a transfer instruction input terminal as described later. This is a transfer register that stores read data from the memory cell array 1 in transfer mode and holds it for at least two memory cycles. The multiplexer 13 is equipped with normal data writing means and data reading means, and in the normal mode, data is exchanged between the memory cell array 1 and the input/output buffer 10.

When data is read from the memory cell array 1 during the transfer mode, it is passed to the transfer register 12, and when data is written to the memory cell array 1 during the transfer mode, the transfer register 12 is switched to the booter. It is. In addition, various control signals RAS, W
Input terminals such as E are completely omitted from illustration.

Next, the operation of the memory will be explained with reference to FIG.

The above memory is used as the main memory of the computer, and the CPU
For example, a third
When transferring data as shown in the figure, first
CP in RAS (row address strobe) cycle I of
The transfer mode instruction input from U becomes active (transfer mode) for a certain period of time.

At this time, the Okaya of the memory cell at the address specified manually is read out and transferred to the transfer register 12 via the multiplexer 13. Next, in the second RAS cycle (2), the WE (write enable) signal input from the CPU becomes active (write mode) for a certain period of time, and the transfer mode instruction input also becomes active for a certain period of time. At this time, the contents of the transfer register 12 are transferred to the memory cell at the address specified by the address input to the multiplexer 13.
It is transferred (written) via . By repeating such operations according to the number of transferred data, data transfer between memory cells is performed without the intervention of the CPU.

In addition, in the normal mode, the transfer mode instruction input is inactive, the input data of the input buffer 10 to the memory cell is selected, and the data output from the memory cell is output to the input/output buffer IQ. Ru.

Note that the third RAS cycle lI [Fl,
Activating a transfer mode instruction input in one RAS cycle, transferring the read data from the memory cell at the current address to the transfer register 12, and then changing the address during the transfer mode and activating the WE signal. This figure shows how the control is operated to write the contents of the transfer recorder 12 to the memory cell of the column address after the change. In this way, data transfer between memory cells having the same row address can be performed at a very high speed.

Further, since each component of the semiconductor memory of the above embodiment is formed on the same semiconductor substrate, it is possible to achieve higher speed and lower cost than when the semiconductor memory is divided into a plurality of chips.

[Effects of the Invention] As described above, according to the semiconductor memory of the present invention, data transfer between memory cells is enabled by the memory itself.
When used in the main memory of a computer, the load on the CPU during data transfer within the main memory can be reduced, and the processing speed of the CPU can be increased.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing a part of an embodiment of the semiconductor memory of the present invention, FIG. 2 is a timing diagram showing the data transfer operation between memory cells in FIG. FIG. 3 is a diagram showing an example of how data is transferred. 1... Memory cell array, 10... Input/output huffer. 11...Transfer instruction input terminal, J2...Transfer register. J3...Multi 7' l/kusa. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (4)

[Claims] (1) means for writing data from the outside into a memory cell array; means for reading data from the memory cell array to the outside; and storing data read from the memory cell array during a transfer mode instructed by a transfer mode instruction input. A semiconductor memory comprising: a transfer register for holding at least two memory cycles in a transfer mode; and means for writing the contents of the transfer register into the memory cell array when a write command is given during a transfer mode. (2) A memory cycle in which data is stored in the transfer register and a memory cycle in which the contents of the transfer register are written into a memory cell array are consecutive. Semiconductor memory described in Section 1. (3) The storage of data in the transfer register and the writing of the contents of the transfer register to the memory cell array are performed consecutively within the same row address strobe cycle. semiconductor memory. (4) The semiconductor memory according to claim 1, wherein the semiconductor memory is formed on the same semiconductor substrate.