JPH02255923A - Image memory - Google Patents

Abstract

PURPOSE:To enable a CPU to read and write the picture data at random while reading and writing data by preparing an address counter and a data buffer independently of each other and setting the random read/write addresses and a data control part at one time. CONSTITUTION:When a CPU reads and writes each word at random, a prescribed address is written into an address register 6 and allocated to a row decoder 7 and a column decoder 8. When the CPU reads out each word at random, one word of a memory cell array 1 designated by the register 6 is read out to a data register 10 and outputted to the input data Din from a buffer 11 via an output enable OE. In a write mode, the data equivalent to one word which is inputted from the data Din via the buffer 11 is written into a data register 9 and then into the array 1. This writing operation is carried out by a write enable WE. Thus the CPU can read and write at random the image data stored in the array 1.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an image memory in which image input/output and random access from a CPU (central processing unit) or the like can be performed in parallel.

BACKGROUND OF THE INVENTION In recent years, digital image processing has been widely used, and as a result, there has been a demand for image memories that are specialized for the equipment to which they are applied.

An example of a conventional image memory will be described below with reference to the drawings.

FIG. 2 shows a configuration diagram of a conventional image memory.

In FIG. 2, 1 is a memory cell array that stores image data, etc., and 2 is an output buffer that reads one row of data from the memory cell array 1 and outputs the data for each word to serial/L'.

3 is a horizontal/vertical read address counter that is incremented each time data is read from memory array 1 to output buffer 2; 4 is an input buffer that stores one line of serially input data for each word and writes it to memory cell array 1; be. 5 is a horizontal/vertical write address counter that is incremented every time data is written from the input buffer 4 to the memory cell array 1. Also, Din is input data, DOut is output data, OE
is an output enable signal, WE is a write enable signal, CKR is a read clock for sequentially outputting data word by word in the output buffer 2, and OKW
is a write clock for sequentially inputting data word by word in the input buffer 4, HCLRO is a control signal that increments the row address and resets the column address in the horizontal/vertical write address counter 5, and HOLRl is the horizontal/vertical write address VCLR○ is a control signal that increments the row address and resets the column address in counter 3, and VILRl is a control signal that resets the row address and column address in horizontal/vertical write address counter 6.
is a control signal for resetting the row address and column address in the horizontal/vertical write address counter 3.

The operation of the image memory configured as described above will be explained below.

First, the input data Din is serially taken into the input buffer 4 word by word by the write clock CXW. When an appropriate timing HCLRo is input, the data taken into the input buffer 4 is transferred to the memory cell array 1 indicated by the horizontal/vertical write address counter 5, and the row address is incremented by one. After writing to an appropriate row address, when VCLKO is input, the horizontal/vertical write address counter 5 is reset and writing is performed from the beginning of the memory cell array 1. Similarly, the output data Dout is serially output from the output buffer 2 word by word in response to the read clock OKH. When HCLR1 is input at an appropriate timing, data is transferred from memory cell V7 Ray 1 indicated by horizontal/vertical read address counter 3 to output buffer 2, and the row address is incremented by 1. After reading the appropriate line address,
When VCLR1 is input, the horizontal/vertical read address counter 3 is reset and reading is performed from the beginning of the memory cell array 1.

Problems to be Solved by the Invention However, with the above configuration, it is not possible to sequentially write data such as images to the memory cell array,
A problem has been that while sequentially reading data such as images from the memory cell array, data such as images stored in the memory cell array cannot be randomly read or written by a CPU or the like.

In view of the above-mentioned problems, the present invention sequentially writes data such as images to a memory cell array, sequentially reads data such as images from the memory cell array, and uses a CPU etc. to write data such as images stored in the memory cell array. The object is to provide an image memory that can be read and written at random.

Means for Solving the Problems In order to solve the above problems, the image memory of the present invention includes a memory cell array, an address register for randomly accessing the memory cell array in units of words, a row decoder, a column decoder, A write data register for writing data to the memory cell array specified by this address register, a read data register for reading data from the memory cell array specified by the address register, and a read data register for writing data to the write data register and from the read data register. An input/output buffer for controlling read data, a horizontal/vertical write address counter for sequentially writing image data from a camera, etc. into the memory cell array, and an input buffer for temporarily storing several words of image data. Equipped with horizontal/vertical read address counters for sequentially reading data from the memory cell array, and an output buffer that outputs several words of data read from the memory cell array word by word by the horizontal/vertical read address counters. It is.

According to the above-described configuration, the present invention uses a horizontal/vertical write address counter and an input buffer for storing several words for sequential input such as image data, and a horizontal/vertical read address counter and a number for sequential output to a display device, etc. The output buffer that stores words is also
Random reading and writing with the CPU etc. is performed by the address register, row decoder, column decoder, write data register, read data register, and input/output buffer, respectively, so that data such as images can be written to the memory cell array in the J-kensha μ. While data such as images is sequentially read from the memory cell array, data such as images stored in the memory cell array can be randomly read or written by a CPU or the like.

Embodiment Hereinafter, an image memory according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of an image memory in an embodiment of the present invention.

1 to 6 and D in , Dou
t.

CKR, CKW, HOLRO, HCLRl.

VCLRO, "/CLR1 are the same as the conventional example shown in FIG. 2. 6 is an address register, 7 is a row decoder that indicates the address in the row direction of the memory cell array 1, and 8 is a column that indicates the address in the column direction of the memory cell array 10. Decoder, 9 is a write data register for 1 word of write data from the CPU, etc., 1o is a read data register for 1 word of read data to the CPU, etc., 11 is a CPU
An input/output buffer that controls the flow of data so that data does not collide when the U etc. writes data, and so that data is output correctly when the CPU etc. reads it. OE is a memory that the CPU etc. WE is an output enable that sets the input/output buffer 711 to output mode when reading data from the cell array 1, and a write enable that enables a write operation when the CPU or the like writes data to the memory cell array 1.

The operation of the image memory configured as described above will be explained with reference to FIG.

First, the input data Din is serially taken into the input buffer 4 word by word by the write clock CKW. When HCLRo is input at an appropriate timing, the data taken into the input buffer 4 is transferred to the memory cell array 1 indicated by the horizontal/vertical write address counter 6, and the row address is incremented by one.

After writing to the appropriate row address, VCLKO
When inputting , horizontal/vertical write address counter 5
is reset, and writing is performed from the beginning of the memory cell array 1. Similarly, the output data Dout is serially output word by word from the output buffer 12 using the read clock CKR. HCLR at appropriate timing
When l is input, data is transferred from the memory cell array 1 indicated by the horizontal/vertical read address counter 3 to the output buffer 2, and the row address is incremented by one. After reading to an appropriate row address, when VCLR1 is input, the horizontal/vertical read address counter 3 is reset and reading is performed from the beginning of the memory cell array 1.

When randomly reading or writing one word from the CPU, etc., a predetermined address is written to the address register 6, distributed to the row decoder 7 and column decoder 8, and one specified word from the memory cell array 1 is selected. be done. When reading, one word of the memory cell array 1 specified by the address register 6 is read into the read data register 1o, and outputted from the input/output buffer 11 to Diyl by the output enable /L10E. When writing, one word of data input from Din through the output buffer 11 is written to the write data register 9, and then written to the memory cell array 1 specified by the address register 6. Data writing control is performed by write enable/L/WE.

As described above, according to this embodiment, horizontal/vertical read address counters, horizontal/vertical write address counters, read data buffers, and write data buffers for serial input/output are provided separately for the same memory cell array, and By providing the same address control unit and data control unit that support random reading and writing, it is possible to sequentially write data such as images to the memory cell array or read data such as images sequentially from the memory cell array. data such as images accumulated in the memory cell array while
It can be read or written randomly using a PU or the like.

Effects of the Invention As described above, according to the present invention, data such as an image is sequentially written into a memory cell array, and data such as an image is sequentially read out from the memory cell array, so that images accumulated in the memory cell array can be processed. It is possible to read and write data randomly using a CPU or the like, which has great practical effects.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an image memory according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional image memory. 1...Memory cell array, 2...Output buffer, 3...Horizontal/vertical read address counter, 4...Input buffer, 5...Horizontal /Vertical write address counter, e...Address register, 7...Row decoder, 8...
Column decoder, 9...Write data register,
1o...Read data register, 11...
...Input/output buffer, Din...Input data, Dout...Output data, Ox...
Output enable signal, WTL...Write enable signal, CKR...Read clock, CKW...Write clock, HCLRO
...Horizontal reset signal 0SHCLR1...
...Horizontal reset signal 1, VCLRO...Vertical reset signal o, VCLR1...Vertical reset signal 1゜Name of agent: Patent attorney Shigetaka Awano and 1 other person 1st
Diagram E

Claims (1)

[Claims] a memory cell array, an address register that randomly accesses the memory cell array in word units, a row decoder, a column decoder, a write data register that writes data to the memory cell array specified by the address register, and a write data register that writes data to the memory cell array specified by the address register. a read data register for reading data from the memory cell array, an input/output buffer for controlling data written to the write data register and data read from the read data register, and an input/output buffer for sequentially writing image data from a camera or the like to the memory cell array. A horizontal/vertical write address counter, an input buffer that temporarily stores several words of the image data, a horizontal/vertical read address counter that sequentially reads data from the memory cell array, and the horizontal/vertical read address counter An image memory comprising an output buffer that outputs several words of data read from a memory cell array word by word.