SU982094A2 - Buffer storage - Google Patents

Description

(5) BUFFER RECORDING DEVICE

The invention relates to computing and can be used in communication technology and computing, in particular, to interface an asynchronous source and receiver of information. According to the main auth. No. 750565, a buffer memory device (OVC) is known, which allows for independent recording and reading of information, read pulses and clock pulses of a RAM can be asynchronous. This device contains number registers, information inputs and outputs which are connected to data inputs and the first inputs of subsequent rewrite gates, the control record register each bit of which consists of three gates, the first inputs of which are connected to the corresponding clock buses of the auxiliary trigger. a trigger, a read trigger, and a read valve, the first inputs of which are connected to the read bus. The first output of the main trigger of the control register is connected to the second input of the first valve, the output of which is connected to the second inputs of the corresponding rewriting valves and the first input of the auxiliary trigger, the output of which is connected to the second input of the third valve, the output of which is connected to the reset input of the corresponding number register and to the second the main trigger input, the output of the read valve through the main trigger of the last bit of the control register is connected to another input of the additional trigger, the output D which is connected to the second input of the read valve, the third input of which is connected to the clock bus, the second output of the main trigger of each bit of the control register of the record is connected to the third input of the first valve of the subsequent discharge, the output of which is connected to the input of the second valve, connected to the second valve to the second input of the auxiliary trigger, and the output of the third valve of each bit is connected to the first input of the main trigger of the previous bit of the control register of the record 11}, the disadvantage of this device and the clock frequency of information entry limits the rate of advancement of information on the registers of the numbers of LPD, since the clock frequency of the OVC must be synchronous to the write pulses, which causes a delay in the information of the RAM, which is greater, the lower the clock frequency of information and more registers of numbers in the RAM. The purpose of the invention is to increase the speed of the buffer storage device. The goal is achieved by introducing a second and third additional triggers and a second additional valve into the device, the first input of which is connected to the first input of the second additional trigger and the write bus, the second and third inputs of the second additional valve are connected respectively to the clock bus and to the output the second additional trigger, the second input of which is connected to the first output of the third additional trigger, the first and second inputs of the third additional trigger are connected respectively but to the output of the second auxiliary valve and to the output of the third valve of the control register, the second output of the third additional trigger is connected to the first input of the first valve of the first discharge of the control register of recording. The drawing shows a functional diagram of the proposed device. The device contains T-l digit registers connected by rewriting gates, a control register of 3 entries ,; including the main triggers connected to the inputs of the first gates whose output is connected to the inputs of the second gates 6-b, auxiliary triggers whose inputs are connected to the gates of the gates and 6-6, and the gates connected to the inputs of the third gates 8-8, trigger 9 read, the output of which connected to the input of the read valve 10, the output of which 4 is connected to the input of the main trigger C, and the output of the main trigger connected to the second input of the trigger 9 read, and the second additional trigger 11 of the lock, the third additional trigger 12 record and, a second additional recording gate 13, the output of which is connected to the input of the third additional trigger 12, whose outputs are connected to the input of the first valve S of the first valve 5 of the first discharge of the control register and to the input of the second additional lock trigger 11, the output of which is connected to the input second additional valve 13 entry. To the inputs of the valves 5 and 6 is connected bus l4 clock. Impulses TI. To the inputs of the valves 13, 8 and 10 is connected bus 15 clock pulses TI2, To the input of the valve 13 and the input of the additional trigger 11 is connected bus 16 record information. To the input of the trigger 9 Iyentil 10 is connected the readout bus 17, and the outputs of the S-S gates are connected to the inputs of the rewriting gates 2-2 via inverters 18-18. The valve outputs are connected to registers f — the number of ANDs to the second inputs of the main triggers k -k of the corresponding bit and to the direct input of the main triggers f- the preceding bit of the control register. The output of the valve 8 is connected to the second input of the main trigger. The device works as follows. Bus 1 if and 15 clock pulses continuously receive a series of clock pulses TI1 and TI2, respectively, shifted in phase one relative to another. In the initial state, from trigger 11 to valve 13, from trigger 12 to trigger 11, from trigger 4 to valve 5 and from trigger 9 to valve 10, a high potential flows. To write information to the bus 16, a pulse arrives that confirms the state of the trigger 11 and, together with the first pulse TI2, through the valve 13 switches the trigger 12, which outputs a high potential to the valve 5 and switches the trigger 11, which removes the high potential from the valve 13 and blocks the write pulse. The first after the switching of the trigger 12 pulse TI1 through the valve 5 and the valve 2 writes into the register 1 the first-bit word, at the same time the auxiliary trigger T of the controlled register switches and supplies a high potential to the valve 8. The second pulse TI2 switches the trigger 12 through the gate 8 which removes high potential from valve 5 and supplies high potential to the trigger 1 This same pulse TI2 switches the trigger through valve 8. The trigger also removes high potential from fan 5 and supplies high potential to valve 5. Pause between pulses writes trigger 11, which supplies high potential to valve 13. A second TMt pulse through valve 5 and valve 7 writes the word to register 1, simultaneously control register trigger 7 switches and supplies high potential to valve 8. The third impulse ТИ2 through the gate 8 resets the register 1, switches (and Г triggers (- and so that the valves 5 and 5 receive respectively high and low potential. With the same third pulse itH2, if the next write pulse arrives, the valve 13 switches trigger 12, which gives a high potential to valve 5 The fourth pulse TI1 through gate S and B writes a new word to the register AND, If the write pulse does not come or the duration of the write pulse is much longer than the duration of the pulses Till (TI2, then new words to register 1 not recorded under the influence of the clock signals TH1 and TI2, the word moves along registers 1-1 and is fixed in the h-bit. A new word is written when the next write pulse arrives. In the case when due to asynchronous write pulses and clock pulses write pulse Overlaps the clock pulse partially, a pulse with a duration (and amplitude) insufficient for switching the trigger 12 is applied to the output of the valve 13, and the described recording cycle is carried out with the following clock pulse ТИ2. Reading information, i.e. updating it in the output register, is a read pulse to the bus 17. The read pulse confirms: gives the trigger status 9 and the valve 10 enters. The pulse TH2, after the read pulse, switches the trigger j, 9 6 which gives a high potential to valve 5 and switches the trigger 9. The trigger 9 removes 10 auto-, cue potential from the valve and blocks the read pulse. The first after BOSAelRctBMfl read pulse is a TI1 pulse. through valve 5 and valves 2, it writes a new w-bit word to register 1. The second impulse ТИ2 through the valve 8 switches the trigger i, which removes the high potential from the valve 5 and confirms the state of the trigger 9. The pause between the read pulses. switches trigger 9. which delivers a high potential to valve 10 and the read cycle repeats when the next read pulse is applied. . From the operation of the device, it can be seen that the 53U allows independent recording and reading of information (tensions, write pulses, reads, clock pulses can be asynchronous. The frequency of clock pulses can be much larger than the frequency of write and read pulses. For reliable operation of the device, the write pulse duration (read ) must exceed the duration of the clock pulse n | W. skva: the last of Q62) or the duration of the pause clock pulses (at 67/2} not less than by the switching time of the additional 11 (9), increased by m the maximum difference between the on and off time of the additional valve 13 (10) which does not exceed the time of the additional valve 13 (10), and the duration of the pause between write pulses (readings must be no less than the switching of the trigger 11 (3), registers 1-1 n-bit numbers can be re-edited to the ft, V and the potential logic triggers on the tE-triggers. The private write register can be multi-cycle. invention buffer memory device auth.St. ff 750565, distinguished by the fact that, in order to improve the speed of the device, it introduced the second and third additional triggers and the second additional gate, the first input of which is connected to the first input of the second additional trigger and to the recording bus, the second and third inputs of the second additional The valve is connected respectively to the clock bus. And to the output of the second additional trigger whose second input is connected to the first output of the third additional trigger, the first and second inputs of the third additional trigger and are respectively connected

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to the output of the second additional valve and to the output of the third valve of the first discharge of the control register of the record, the second output of the third additional trigger is connected to the first input of the first valve of the first discharge of the control register of recording.

Sources of information taken into account in the examination

1. USSR author's certificate W 750565,. G P S 19/00, 1976.

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Claims (1)

Claim Auto Storage Buffer No. 7 $ 05b5, which is distinguished by the fact that, in order to increase the speed of the device, the second and third additional triggers and a second additional valve are introduced into it, the first input of which is 55 Ί the second is connected to the first input of the second additional trigger and to the recording bus, the second and third inputs of the second additional valve are connected respectively to the clock bus. And to the output of the second additional trigger, the second input of which is connected to the first output of the third additional trigger, the first and second the inputs of the third additional trigger are connected respectively to the output of the second additional valve and to the output of the third valve of the first category of the recording control register, the second output of the third additional 5 threads The first trigger is connected to the first input of the first valve of the first category of the control register of record.