JPS5855485Y2 - information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus having means for generating an internal timing signal based on a basic clock signal.

An information processing device usually has a central processing unit (CP) as shown in Figure 1.
U) 10, program memory unit (ROM) 20,
The basic components are a readable/writable memory device section (RAM) 30 and an input/output device section (Ilo) 40, and are connected to each other by an address bus 50, a data path 60, and a read control signal line RD.

Conventionally, in such information processing devices, when the basic clock frequency of the entire device was increased for the purpose of shortening data processing time, problems occurred in the timing of data transfer due to differences in response speed of each device. .

In other words, the processing and response speed of CPU 10 can be easily increased, but at this time, other devices such as 1040
It may not be possible to respond to the speed of l0.

In such a case, lower the clock frequency of the entire device to match the device with the slowest response speed, or
Alternatively, the CPU 10 can be
It was necessary to synchronize the devices by initiating the pause state of l0 for each input/output cycle of the device with each device.

However, if the CPU 10 is stopped each time data is input/output according to the device with the slowest processing speed, the processing speed is naturally limited and high-speed processing cannot be achieved.

An object of the present invention is to provide an information processing device that has the fastest response speed and does not reduce the processing speed of the device.

The present invention is an information processing apparatus having means for generating a timing signal for internal control based on a basic clock signal, and is characterized by having means for delaying generation of the timing signal for internal control by a predetermined period.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an internal timing signal generating means of an information processing apparatus showing an embodiment of the present invention.

In order to simplify the explanation, it is assumed in this embodiment that the CPU has the fastest response speed, and furthermore, this CPU receives two basic clock signals φ1. Three different internal timing signals T1 to T3 are generated from φ2, and these three internal timing signals T1 to T3 that constitute each status period are generated from φ2.
It is assumed that one program instruction is executed by T3.

Therefore, these three internal timing signals T1 to T3 may be sequentially outputted, respectively.

As is clear from the figure, the internal timing signal generating means consists of transistors Q1 to Q1 through which clock signals φ1 to φ2 are alternately applied to the gate electrodes to sequentially shift the input signals.
Q5, and inverters ■1 to ■7 connected in series between each transistor, and the first inverter ■1. Third
Internal timing signals T1 . Create T2゜Tw, T3.

In this case, the signal input to the inverter 11 to generate the timing signal may be any input signal that can detect the end of each program command and set the pulse width of the timing signal T1. A timing signal is created to execute the next program instruction.

Furthermore, in order to reliably set the pulse width of the timing signal T1, a transistor to which the clock 6 is applied to the gate may be provided before the inverter 11.

Each timing signal pulse is obtained in synchronization with the rising edge of clock signal φ2, so its pulse width is
This corresponds to one period of 2.

Furthermore, it has a flip-flop 5 composed of NOR gates 1 and 2, the output of each of which is input to a corresponding NOR gate 3.4.

An inverted clock signal .phi.1 is applied to the other input terminal of this NOR circuit 13.4 via an inverter I8.

The output of the NOR gate 4 is applied to the gate electrode of the transistor Q5 connected to the inverter I3 that generates the timing signal Tw, and the output of the NOR gate 3 is applied to the inverter 3 and the inverter.

Transistor Q via another electrical path connecting
Added to gate 7.

When the internal timing generation means is configured as described above, the flip-flop 5 is controlled to set the output of the NOR gate 3 to H.
level and turns transistor Q7 into a conductive state, the internal timing signal T1. T2° and T3 are created sequentially.

On the other hand, transistor Q7 is cut off and transistor Q5 is cut off.
By applying a control pulse synchronized with clock φ1 to T1. T2. Internal timing signals are generated in the order Tw and T3.

This operation will be explained below with reference to the timing diagrams of FIGS. 3 and 4.

FIG. 3 shows a timing signal T1. which is normally generated during program processing within the CPU 1 or when data is transferred between peripheral memories 2, 3, etc. that have fast response speeds. T2. T3
It shows.

In FIG. 2, by resetting the flip-flop 5, L and H are output from each NOR gate 1 and 2, respectively.
The level will be output.

Therefore, the output of the NOR gate 4 connected to the gate of the transistor Q5 is in an inhibited state, that is, outputs an L level, thereby cutting off the signal transmission path from the inverter (2)5 to the inverter (2)6.

On the other hand, in the transmission path connecting the inverters I3 and T6, the opening and closing of the transistor Q7 is controlled in synchronization with the rising edge of the clock φ1 sent through the NOR gate 3, so that the timing signal T1. T2. Made in the order of T3.

If the address signal AB is output from the CPU 1 to the memory 3 during the period of the timing signal T1, and if the response speed of the memory 3 is fast, the address signal AB from the memory 3 to the CPU 1 corresponding to the address signal is output from the memory 3 during the data read period TAc1.
data is read out, and the device can perform high-speed processing (Figure 3).

Furthermore, when the CPU 1 performs data transfer with the peripheral device 4, if the response speed of the peripheral device 4 is slower than the processing speed of the CPU 1, input signal lines 6 and 7 of the flip-flop 5 are By applying L and H level signals, respectively, the path connecting inverter Ij and T6 is cut off, and by applying clock φ1 to transistor Q5, a timing interval can be established between the generation of timing signals T2 and T3. can.

Therefore, the timing at which the CPU 1 reads data from the peripheral device 4 can be substantially delayed (TAC2).

On the other hand, the timing signal Tw generated during data transfer with the peripheral device 4 can also be used for other processing purposes within the CPU 1, eliminating the need to stop the CPU 1 by external operation as in the past (FIG. 3).

Therefore, according to this embodiment, it is only necessary to create the delay timing Tw and achieve synchronization only when data is transferred to a device with a particularly slow response speed, and for a device with a fast response speed, the CPU can be stopped as in the conventional case. Data transfer can be performed at high speed.

It is also clear that it is only necessary to control the input signal of flip-flop 5 in order to obtain the desired internal timing signal.

Here, a major feature of the present invention is that the flip-flop 5 can be controlled by program data read from an internal memory or the like during program execution.

In other words, if the flip-flop control data is incorporated into the software in advance, the generation timing of the internal timing signal can be automatically changed when data is transferred to a device with a slow response speed or during program control. Efficiency can be greatly increased.

In this embodiment, a shift register configuration is shown as the internal timing signal generating means, but even if the configuration has a plurality of stages of counter circuits connected in series, each counter, for example, the second stage counter and the fifth stage counter, may be replaced with a transistor. By connecting separately via Q7, T1. T2. T3. T4. T
The timing signal T1. T2. The timing signal T5 can also be generated simply by program-controlling the flip-flop, making it possible to freely set the write time or read time of the data.

Furthermore, in this embodiment, each timing signal T, T2
．． It may be configured such that a timing signal Tw is obtained in the middle of each of T3.

In this case, each timing signal T1. T2. It is clear that T3 is all output delayed by the same period (Tw).

In this way, a circuit for obtaining a timing signal Tw can be inserted at an appropriate location.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of an information processing device, FIG. 2 is an internal timing signal generation circuit showing an embodiment of the present invention, and FIGS. 3 and 4 are timing diagrams showing operating states, respectively. be. DESCRIPTION OF SYMBOLS 10... Central processing unit part (CPU), 20... Program memory device part, 30... Readable and writable memory device part, 40... Input/output device part, 50... Address bus, 60... ...Data bus, φ1. φ2...
Clock signal, T1. T2゜T3...Internal timing signal, RD...Read signal, TA61. TA62...
・Reading time, 1 to 4...NOR gate, 5...
Flip-flop, 6, 7...program data,
■1~I8...Inverter, Q1~Q7...Transistor.

Claims (1)

[Scope of utility model registration request] In an information processing device having a timing control signal generation circuit formed by connecting a plurality of circuits in series to generate a timing control signal of a predetermined width in response to a clock pulse, the output of the first timing control signal generation circuit is immediately outputted. A first path for supplying to a subsequent second timing control signal generation circuit, and a second path for supplying to a subsequent third timing control signal generation circuit by skipping the second timing control signal generation circuit. By interposing a gate circuit in this second path, the gate circuit can be turned on and off, thereby changing the number of timing control signals that are successively generated. An information processing device characterized by: