JPS5911941B2 - Arithmetic control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a subroutine control method for electronic equipment in which a stack register holds a smaller number of bits than the number of bits corresponding to an address flip-flop (program counter).

In conventional arithmetic control systems, providing a stack has the following drawbacks.

First, in a read-only memory random access memory (hereinafter referred to as ROM-RAM) system, which is a system that performs bit processing, stack flip-flops corresponding to address flip-flops are required as many as the number of stack stages.

For this reason, as the number of stack stages increases, the number of input control gates of the stack flip-flops increases, resulting in a disadvantage that the circuit configuration of the electronic device becomes complicated. In addition, if a read-on memory shift register (ROM-SR) method is adopted in which a shift register is used instead of the ROM-RAM RAM, and one instruction is processed in one word, the same result can be obtained without using a stack. When using a routine repeatedly, it is determined by flags. In this case, the number of ROM steps increases significantly, and the circuit configuration becomes complicated. Furthermore, if a stack is provided, the number of stack bits corresponding to the address flip-flop is required for one stage of the stack. Therefore, the circuit configuration becomes complicated. An object of the present invention is to provide an arithmetic control system for electronic equipment that requires a simple circuit configuration, in order to solve the problem that the circuit configuration becomes complicated when the stack is provided. This is a subroutine control method in which the stack register holds a smaller number of bits than the number of bits corresponding to the address flip-flop. Examples will be described below with reference to the drawings.

FIG. 1 is a circuit configuration diagram of an embodiment according to the present invention.

These include subroutine registers 1 to 9, which are stack registers, gate units 18 to 25 to which inverters 10 to 1T are connected, address flip-flops (program counters) 30 to 40, and flip-flops 4
1 to 48 and each gate 50 to 78. Subroutine registers 1 to 9 and flip-flops 41 to 48 are controlled by clock pulses φ1 and φ2. The output signals S4-2 to S2-3, which are serial signals of the registers 1 to 8, are respectively input to gate unit ports 8 to 25 having the same configuration and converted into parallel signals, and the output parallel signals are Furthermore, it is added to each address flip-flop 33-40. ROM output signals 04 to 01 of 01 to 014
1 is applied to each gate unit 18-25, and output signals 012, 013, 014 are applied to address slip-flops 30, 31, 32. Further, they are illustrated as a subroutine jump command signal α and a return command signal β.

Address flip-flops 30 to 34 are controlled by clock pulse φc, and address flip-flops 35 to 40 are controlled by clock pulse φA. Flip-flop 41 to 4
Reference numeral 8 converts the parallel signals of the output signals A3 to AIO of the address flip-flops 33 to 40 into serial signals.

The TA signal is a 1-bit signal used to convert a parallel signal into a serial signal, and is generated only during a subroutine jump. The output of the gate 57 is assumed to be a P signal. The explanation will proceed assuming that, for example, 8 bits are held in the stack register. In loop A, when subroutine jump command signal α and return command signal β are not applied, subroutine registers 1 to 9, gate 51,
This is a loop that cycles through 54.

Loop B is formed by subroutine registers 1 to 6 gates 52 and 54 in order to shift to the right by 2 digits (8 bits) when a return command + signal β is added. Loop C is for shifting 2 digits to the left (8 bits) in order to store the original address (8 bits) when subroutine jump command signal α is applied, and subroutine registers 1 to 9 and flip-flop 1 48 and each gate 53, 54, 55 to 78. FIG. 2 is an explanatory diagram of the configuration of subroutine control.

In this embodiment, main routine A has 4 pages and 9 steps, and has been upgraded to 13 pages and 1 step of subroutine B, and then moves to subroutine B.
At the page 6 step, the process further moves to the 8 page 5 step of subroutine C. Then, at step 14 on page 8 of subroutine C, 13 of subroutine B
Assume that the process returns to page 5 step. Furthermore, at step 28 on page 13 of subroutine B, the transition is made to step 11 on page 4 of main routine A. It is assumed that the calculation control configuration is as described above. now,
The following explanation assumes that one word is 64 bits and the stack is two stages. At this time, subroutine registers 1 to 9 are 64.
It's bit. Address flip-flop 30 to 40
Table 1 shows the states of the output signals A to A1O in the arithmetic control shown in FIG. Table 2 shows the states of the stack registers corresponding to Table 1.

The explanation is given assuming that 8 bits of the output signals A3 to A, O are held in the stack register every 4 bits. Further, Table 3 shows the explanations of ROM output signals 01 to 014, which are instruction codes.

Output signals 03 to 0 specify pages for page jumps and subroutine jumps.

010 to 014 designate the next address. Table 3 shows methods for determining page jumps and subroutine jumps, including a method based on the output signal status of the 1-address flip-flop 30, and a method using 2 instruction codes.

Note that * is a freely specified code. In Table 3, the page jump instruction is an instruction to jump up the program in the ROM page by page and execute a predetermined step, and the ROM output signal 010203 is '010'' and the signal 01
4 is 0'', that is, it is output when the next address is specified as an even address, and output signals 03 to 0 indicate the page,
Steps are designated from 010 to 014.

Similarly, the subroutine jump instruction outputs the output signal 0102
03 is '010' and the output signal 014 is '1', that is, it is output when the next address is specified as an odd address.

When main routine A is executed and the jump-up address 4 pages 9 steps to subroutine B is reached, the next address specifies the start address 13 pages 1 jump of subroutine B.

At this time, the ROM output signals 01 to 0,4 are as shown in Table 4. Since output signals 0 and 4 become 1, a subroutine jump command signal α is generated.

Therefore, subroutine registers 1 to 9, flip-flops 41 to 48, and gates 53, 54, 55 to 7
8 forms a C loop. Then, the address flip-flop parallel output signal A3 to AlO
is converted into a serial signal by the TA signal (timing Tlt, assuming digit time signal T1 and bit time signal t1). The signals are converted into serial signals by gates 55 to 78 and held in subroutine registers 1 to 9, which function as stack registers. At this time, parallel output signal A. Rather than holding all 11 bits from A3 to AIO, 8 bits from A3 to AIO (in the above example, information indicating the fourth page of main routine A) are held. Output signal A. The 3 bits A2 to A2 (step information other than the 9th step on the 4th page of main noretin A) are not specified at this time, and are called from the ROM in response to the return command of subroutine B when returning to the return address. , are supplied to address flip-flops 30, 31, and 32. At the same time, the upper 8 bits of the above stack register are also supplied to the end address flip-flops 33 to 40, and these 11 bits of information are used to eventually determine the return address (in this case, steps other than the 9th step on the 4th page of main routine A). can be determined. At this time, the data is stored in the stack register in the hexadecimal code format of (S2, Sl)=(1, 1) as shown in Table 2. Regarding this, in the case of the instruction to jump to subroutine B shown in Table 1, the binary coded decimal numbers AlO to A7 of the address flip-flop correspond to the state of S2 of the stack register, and A6 to A3 correspond to the state of the stack register S2. It corresponds to the state of register S. During the execution of subroutine B, when the 6th step on page 13 is reached, 2
The stack register is shifted to the left by 2 digits (8 bits in this case), so it is held in the format (S4, S3, S2, Sl) = (1, 1, 3, 4). It will be done. The previous states of S2 and Sl in the stack register are shifted to the left and are changed to S2 and Sl in the stack register.
4 and S3, and the output signals A1O to A3 when issuing the JASP command to subroutine C correspond to the new states of S2 and S1 of the stack register.

When the execution of subroutine C ends and the process returns to subroutine B, a return command signal β is generated.

Therefore, loop B is executed and the stack register is shifted to the right while the gate units 18-25 convert the serial signals into parallel signals and define the states of the address flip-flops 33-40. The states of address flip-flops 30 to 32 are 8 in subroutine C.
At the page 14 step, ROM output signals 0, 2, 013, 0, 4 specify the next address of the return instruction.
Specified by

If the return instruction in subroutine C is the ROM output signal (012-013?014) 0 (120'1), that is, (A2, Al, AO) = (1, 0, 1), the return address in subroutine B is is page 13 5
It is designed to be a step. Subroutine B
Similarly, the return to main routine A from 4 pages 1
Made in 1 step. Figure 3 shows these time charts. In the subroutine control configuration described above, it is necessary to pay attention to the following points.

[1] The first address in each subroutine must always be an odd number.

[2] The return address is determined by the upper 8 bits held in the stack register and the lower 3 bits specified by the return instruction.

Since the return instruction of the subroutine specifies the three bits (AO, Al, A2) of the address flip-flop, it is not possible to select a free address as the return address. Regarding [1], as shown in Table 3, the output signal A of the 1-address flip-flop 30, excluding the codes for the page jump instruction and subroutine jump instruction.

According to the determination method described above, the codes of ROM output signals 01, 02, and 03 can be used for other instructions. However, 2
In the method of determining by instruction code, this is used for subroutine instructions, so to hold instructions of these codes, R
Requires expansion of OM capacity. The first determination method is not limited to the method using the output signal 014 as described above, and any of the output signals 010 to 014 can be used.

In the first determination method, specifying the jump destination is achieved by specifying a return address for the subroutine.

This method does not particularly require increasing the ROM capacity, and has the effect of simplifying the circuit configuration. To explain [2], the lower 3 bits of the return address are converted to ROM output signals 012, 013, 014 by the return instruction.
Specified by

For example, the program steps (line numbers) of main routine A are grouped or paged into eight steps. That is, the steps are grouped into A group (0 to 7 steps), B group (8 to 15 steps), C group (16 to 23 steps), and D group (24 to 31 steps). In other words, when jumping to a subroutine from 3 steps in group A, the return address will be any step in group A excluding 3 steps, and this designation is determined by the 3 bits 012, 012, and 012 derived from the ROM by the return instruction of the subroutine. It is specified by the information of 013 and 014 (see FIG. 1).

Conventional subroutine return commands such as ROM-RA
In the case of the M method, the next step after the jump address is the return address, but the present invention is different in this point.

In the subroutine control system of this embodiment, since the subroutines are divided into groups of 8 steps, it is not possible to issue the subroutine jump command more than 8 times in a row.
In the above explanation, the stack register has 8 bits and the return instruction has 3 bits, but when the address flip-flop becomes 10 bits, the stack register has 8 bits.
It is also possible to take the form of 2 bits for the return command. In other words, the format can be optimized in terms of system design. FIG. 4 is a circuit diagram of another embodiment of the present invention.

In the embodiment shown in Fig. 1, different circuit configurations were used for mutual conversion between serial and parallel signals, but in the embodiment shown in Fig. 4, an address flip-flop was installed. This is done using a common control gate by separately controlling the signals. The circuit shown in FIG. 4 is composed of subroutine registers 80 and 81 which are stack registers, address flip-flops 82 to 92, and gates 93 to 121. Subroutine registers 80 and 81 are controlled by clock pulses φ1 and φ2, and address flip-flops 82 to 89 are controlled by clock pulses φA or φB. Furthermore, address flipflops 90, 91, and 92 are controlled by a clock pulse φC. ROM output signals 04, 05 to 011 are input to gates 99, 102 to 120, and 0, 2, 013, 0, and 4 are input to address flip-flops 90, 91, and 92, respectively.

Subroutine jump command + signal α, return command signal β
Illustrated as This circuit operation is performed by subroutine registers 80, 81, gates 93, 9 when subroutine jump command signal α and return command signal β are not generated.
The circulation loop A formed at 7 is taken. When the subroutine jump command signal α is generated, the subroutine registers 80 and 81 and the address flip-flop 8
The loop C formed by gates 2 through 89 and each gate 96, 97, 98 through 121 causes the stack register to be shifted to the left by two places.

When the return command signal β is generated, a loop B is formed by the subroutine register 80 and gates 95 and 97, and the stack register is shifted to the right by two places.

Gates 98, 100, 101, 103. ~119,1
21 converts the serial signal into a parallel signal. Further, the ROM output signals 04 to 014 are output to the gates 99, 100, 102, 1 at the timing of Tl5.
Address flip-flops are designated by 03 to 120 and 121. FIG. 5 is a time chart in this embodiment.

As described above, the present invention is a subroutine control system that causes the stack register to hold a smaller number of bits than the number of bits corresponding to the address flip-flop.

This control method simplifies the circuit configuration, allows easy subroutine control, and has the effect of reducing the number of ROM steps.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of an embodiment according to the present invention, FIG. 2 is a configuration explanatory diagram of subroutine control, FIG. 3 is a time chart in one embodiment, and FIG. 4 is a circuit diagram of another embodiment. , FIG. 5 is a time chart in another embodiment. 1 to 9, 80, 81... Subroutine registers, 18 to 25... Gate unit, 30
40-40, 82-92...Address flip-flop, 41-48...Flip-flop, 10-17...Inverter, 50-78
, 93 to 121... Gate.

Claims (1)

[Claims] 1. When jumping from a certain step in the first routine to a second routine, specify the program page or group among the multiple bit information that specifies the program page or group and its step in the first routine at that time. In addition, when returning from the second routine to the first routine, the bit information of the stack register is stored in the address flip-flop (program counter) in response to a return instruction. ), and the step different from the step in the first routine at the time of the jump is derived from the read-only memory as information of the remaining lower multiple bits and supplied to the address flip-flop, and the output content of this address flip-flop is An arithmetic control system characterized in that the second routine returns to a predetermined position of the first routine in accordance with the above.