JPS63249208A - Sequence controller - Google Patents

Abstract

PURPOSE:To improve a processing speed by reading out a state of an internal register, and writing it in an internal register of the next processor, before the next processor operated by synchronizing with a clock generator processes a program. CONSTITUTION:Each processor 1, 3 synchronizes with a clock generator, and executes and processes successively an instruction supplied from execution program store memories 2, 4. In this case, prior to the execution, a state of an internal register of a pre-stage processor is always written, therefore, they are operated as one piece of processor virtually. Accordingly, it will suffice that a sequence program written for one piece of sequence processing processor is stored only successively in each execution program store memory 2, 4 in order of execution of the processor, and a program which has considered mutually operations of plural processors 1, 2 is not required. Also, each processor 1, 2 executes an access to each execution program store memory 2, 4, therefore, a memory of a high speed access time is not required. In such a way, the sequence processing speed can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a sequence controller consisting of a plurality of sequence processing processors with readable and writable internal registers.

Conventional techniques There are two ways to speed up sequence processing: increasing the processing speed of the sequence processing processor itself, and dividing the processing using multiple sequence processing processors to increase the overall processing speed. .

FIG. 4 shows a timing chart of a conventional example in the former case. Increasing the processing speed of the processor itself speeds up one instruction cycle. However, since the access time of the memory in which the program is stored does not change, the instruction reading time cannot be faster than the memory access time in which data is output after the memory address is determined. This method requires a memory with very fast access time as the processor itself becomes faster.

FIG. 6 shows a conventional program in the latter case. To perform parallel processing on multiple processors, instructions are needed to exchange data between the processors. However, depending on where these instructions are placed in the program, the sequence processing speed will vary greatly, so careful consideration is required.

Problems to be Solved by the Invention As described above, in conventional sequence controllers, when increasing the processing speed of the processor itself, access between the memory where the program is stored and the processor is increased. The problem is that memory with very fast access times must be used. Furthermore, when processing is divided, a plurality of programs are required that mutually consider the operations of a plurality of processors, and each program becomes complicated.

Means for Solving the Problems In order to solve the above problems, the present invention provides a plurality of sequence processing processors equipped with internal registers from which data can be read and written from the outside, and an execution program is supplied to these plurality of processors. . Memories for storing execution programs of the same number as processors, means for dividing and storing sequence programs in the plurality of memories, a clock generator for synchronizing processing cycles of the plurality of processors, and signals from external I/O. an input circuit for providing the information to the plurality of processors, and an external I/O
The sequence program is divided and stored word by word in a plurality of storage memories, and any processor processes one word of the program from the storage memory. The present invention is characterized in that the state of the internal register is read out each time, and written to the internal register of the next processor, which operates in synchronization with the clock generator, before the next processor processes the program.

Operation According to the above configuration, each processor sequentially executes instructions supplied from the execution program storage memory in synchronization with the clock generator, but the state of the internal register of the preceding processor is always checked before execution. Since the sequence program written for one sequence processing processor appears to operate as one processor, all that is required is to sequentially store the sequence program written for one sequence processing processor in each execution program storage memory in the order in which the processors are executed. get better,
There is no need for a program that mutually considers the operations of multiple processors.

Furthermore, since each processor accesses each execution program storage memory, a memory with high-speed access Φ time is not required.

Embodiment The embodiment shown in FIGS. 1, 2, and 3 includes two sequence processing processors 1 and 3 equipped with readable and writable internal registers, and two execution program storage memories 2 and 4. , a clock generator 5 for synchronizing each processor and a peripheral section, a sequence program storage memory 6, and a CPU for dividing and storing the sequence program in the execution program storage memories 2 and 4;
A sequence controller is composed of a register sharing circuit 8 that mutually reads and writes internal registers of two processors in synchronization with a clock generator, and an input/output circuit 9 that interfaces each processor with Ilo. .

The CPU 7 reads the program from the sequence program storage memory, and stores it alternately one word at a time into the first execution program storage memory 2 and the second execution program storage memory 4, as shown in FIG.

After the program has been stored, the clock generator activated by the CPU 7 runs as shown in FIG.
A reference clock is supplied to the first sequence processing processor 1, and a cross clock whose phase is delayed by half a cycle is supplied to the second sequence processing processor 3.

The first sequence processing processor 1 decodes the instruction outputted from the first execution program storage memory 2 at the rising edge of the reference clock, and reads the information between the I10 data specified by the address also outputted from the memory 2 and the internal register. Logical operations and data output to Ilo are performed via the input/output circuit 9 at the falling edge of the reference clock. Prior to the fall of this reference clock, the second sequence processing processor 3
Since the state of the internal register of is written to the first sequence processing processor 1 via the register sharing circuit 8, the state of the internal register of the second execution program storage memory 4 after the program execution process of one step before is written as a result. This means that a logical operation has been performed between the I10 data and the currently addressed I10 data.

Next, the second sequence processing processor 3 decodes the command output from the second execution program storage memory 4 at the rising edge of a clock that is delayed by a half cycle phase from the reference clock.
Similarly, logical operations between I10 data specified by the address output from memory 4 and internal registers,
Data is output to Ilo via the input/output circuit 9 at the falling edge of a clock delayed by a half cycle phase from the reference clock.

Prior to the fall of this clock, the state of the internal register of the first sequence processing processor 1 has been written to the second sequence processing processor 3 via the register sharing circuit 8, so as a result, the state of the internal register of the first sequence processing processor 1 is This means that a logical operation has been performed between the internal register of the program storage memory 2 after the program execution processing in the step above and the I10 data designated by the current address. Processing is performed while repeating the above operations alternately.

As described above, according to the present invention, one sequence processing processor program is divided and stored in two execution program storage memories for each step, and the two sequence processing processors are shifted in phase by half a cycle, and each storage By executing instructions from memory and writing the state of each processor's internal registers before each processor executes the process, the same sequence program can be used and the memory access time can be reduced compared to a single sequence processing processor. The processing speed can be doubled without changing the settings. The present invention is configured with two sequence processing processors and two execution program storage memories, and not only doubles the processing speed of the sequence controller, but also doubles the processing speed of the sequence controller and the execution program storage memory. Improved by increasing program storage memory.

Effects of the Invention According to the sequence controller of the present invention, as described above, a sequence controller that improves sequence processing speed uses a program for one sequence processing processor and maintains the access time of the program storage memory. A controller can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a schematic diagram of its program storage method, FIG. 3 is a timing chart of its operation, and FIG. 4 is a timing chart of the first conventional example. FIG. 5 is a diagram showing an example of a second conventional program. 1...First sequence processing processor, 2...
...First execution program storage memory, 3...
・Second sequence processing processor, 4...second
Execution program storage memory, 6... Clock.
Generator, 6... Sequence Φ program storage memory, 7... CPU1B... Register sharing circuit, 9... Input/output circuit. Name of agent: Patent attorney Toshio Nakao and one other person＠
1 Figure 10 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] a plurality of sequence processing processors equipped with internal registers that can read and write data from the outside;
Supplying execution programs to these multiple processors,
Memories for storing the same number of execution programs as processors, means for dividing and storing sequence programs in the plurality of memories, a clock generator for synchronizing the processing cycles of the plurality of processors, and an external I/O
an input circuit for supplying signals from the processors to the plurality of processors, and an output circuit for supplying signals from the plurality of processors to external I/O, and transmits sequence programs to the plurality of storage memories word by word. The program is divided and stored sequentially, and each time a given processor processes one word of the program from the storage memory, the state of the internal register is read and the next processor, which operates in synchronization with the clock generator, processes the program. A sequence controller configured to write to an internal register of a processor.