JPS62145444A - Image data recorder - Google Patents

Abstract

PURPOSE:To attain simultaneous processing of read/write with simple constitution efficiently at a high speed by setting a memory area based on control information relating to a write/read outputted from an image input device and an image output device. CONSTITUTION:A write page signal WPAGE and a write clock signal WCLK are given from a device 20 to an address generation block 11 and write data WDATA is given to a write data register 13. A read page signal RPAGE and a read clock signal RCLK are given to the block 11 from a device 30. The signal WDATA of the device 20 is written on an address of an idle bank of a memory block 16 via the register 13 in the timing synchronizing with the clock signal formed by the timing block 12. Further, data corresponding to a memory address is read from the block 16 synchronously with the clock signal outputted from the block 12 and outputted as a signal RDATA to the device 3 via a register 17.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image data recording device that can simultaneously write and read image data without complicating the configuration.

[Conventional technology]

2. Description of the Related Art Some conventional image data recording apparatuses are designed so that, for example, when reading and writing a large amount of image data frequently, it is possible to execute only one of reading and writing. In this case, if the image data is large, it will take a long time to read and write.

Therefore, in order to solve this problem, an image recording apparatus has been proposed that can perform reading and writing simultaneously and can significantly reduce processing time.

[Problem that the invention seeks to solve]

However, in the conventional image data recording apparatus, in order to perform simultaneous processing, the configuration becomes complicated, a special circuit needs to be provided, and the control becomes complicated.

[Means and effects for solving the problem] The present invention has been made in view of the above circumstances, and in order to be able to write and process image data without complicating the configuration, a write memory area is provided. and a memory area for continuous printing is set based on control information output from a plurality of devices, and when the control information satisfies a predetermined condition, each memo 'J
The present invention provides an image data recording device that can simultaneously write and read data to and from a 6i area.

〔Example〕

The image data recording device according to the present invention will be explained in detail below.

FIG. 1 shows an embodiment of the present invention, in which a device to be read (
A) When the write clock signal (WCLK) and write page signal (WPAGE) are applied from 20, the clocks are sequentially counted and a memory write address is generated, and the page signal is successively sent from the device to be written (B). (RPAGE) and a read clock (RCLK) are applied, an address generation block 11 that sequentially counts RCLK to generate a memory read address, and a timing block 12 that generates a timing signal in synchronization with WCLK. a write data register 13 that reads and temporarily stores data from the device (A) based on WCLK; and a refresh control block 14 that executes memory refresh control based on a timing signal given from a timing block 12. and,
A memory control block 15 controls input/output of data to and from the memory block 16 based on output signals of the address generation block 11, the timing block 12, and the refresh control block 14;・
It consists of a memory block 16 into which data from the data register 13 is written, and a read data register 17 which temporarily stores data to be sent from the memory block 16 to the reading device (B) 3Q. The image data recording device 10 having such a configuration is connected between a device (A) 20 that writes data to the device 10 and a device (B) 30 that reads data from the device 10.

In the above configuration, from the device (A) 20, the WPAGE
A signal, WCLK, and a signal are applied to the address generation block 11, and write data (WDATA) is applied to the write data register 13. Also, mounting @ (B) 30
From there, the RPAGE signal and the RCLK signal are applied to the address generation block 11. WPA from device (A) 20
When the WCLK signal is input while the GE signal is rising, the address generation block 11 sequentially counts the WCLK and generates a memory write address. At the same time, WCLK is synchronized with the clock signal generated by the timing block 12, so that the data (WDATA) in the device (A) 20 is sent via the register 13 to designate an empty bank or a read memory bank in the memory block 16. is written to the address of

Similarly, equipment! (B) When the RCLK signal is input to the address generation block 11 during the period when the RPAGE signal from 30 is rising, the RCLK is counted by a counter separate from the counter that counts the WCLK signal, and the memory read An address is generated. The data corresponding to this read address (data already written to the specified memory bank) is stored in the timing block 12.
The device (B) is read out from the memory block 16 in synchronization with the clock signal output from the device (B) via the register 17.
30 as RDATA. In the embodiment shown in FIG. 1, a 250 K-bit DRAM is used as the memory block 16 (total capacity is 4 Mbytes), so a refresh operation is required. executed by

FIG. 2 shows details of the address generation block 11, and the RC
Every time LK is input, count up and RP
A read address counter 101 that is cleared by the AGE signal, and the top four outputs of the counter 101
A decoder 102 decodes bits and outputs a bank select signal (RBS), and the lower 18 bits of the output of the read address counter 101 are sent to a memory of 9 bits each by a timing signal (TRC) given from a timing block 12. A multiplexer 103 that outputs the address (MRA), a flip-flop 104 that latches the RCLK signal, and the flip-flop 104
a flip-flop 105 that synchronizes the output of the read/write start timing (TRW) and outputs successive request flags PR and TN, and a write address counter that counts up every time WCLK is input and is cleared by the WPAGE signal. 106 and the counter 10
A decoder 107 decodes the upper 4 bits of the output of 6 and outputs a bank select signal (WBS), and a decoder 107 decodes the upper 4 bits of the output of the write address counter 106 and outputs a bank select signal (WBS). Row (Roll) address 9 bits and column (Co)
lusn) address 9 bits) MWA, a flip-flop 109 that launches the WCLK signal, and a flip-flop 110 that synchronizes the output of the flip-flop 109 with TRW and outputs a write request flag FW. A comparator 111 that compares the WBS signal and the MWA signal and generates an output signal when both signals match, a Nant gate 112 that takes the logical product of the comparator output, the 7m- signal, and the FW signal, and the output signal of the gate 112. It is composed of a flip-flop 113 that generates an output signal and clears the flip-flop 109 when synchronized with the TRW signal and the TRW signal.

In the above configuration, the read address and write address each consist of 22 bits, and the lower 18 bits of this bit string are used by multiplexers 103 and 108 to create memory addresses MRA and MWA of 9 bits each. Also, read (Read) address and write
(Write) Band select signals RBS and WBS are generated based on the upper 4 bits of the address. Furthermore,
Flags FR and FW are created by synchronizing RCLK and WCLK with TRW. The above signals and flags are output to the memory control block 15.

When RCLK and WCLK are input in the same read and write cycle, and there is a gap of less than a certain value between the write memory area and the read memory area, that is, the read address and write address are in the same bank (RBS=WBS). In some cases, priority is given to reading (Read) and writing (
Write) in the next cycle.

FIG. 3 shows a part of the memory control block 15 (control signal generation part of memory bank B), and
Or game number 51, which takes the logical sum of BS and WBS, and WB
The Nant gate 152, which takes the logical product of S and 7, and the MRA and MWA given by the address generation block 11 are selected by the WBS select signal, and the memory address (
A multiplexer 153 that outputs MAo) to memory bank B0, an output signal of the OR gate 151, and a column timing signal (T
A Nante gate 154 that takes the AND of the output signal of the OR gate 151 and the low timing signal (T,,,'') output from the timing block 12; CAS*wo output from 154 and CAS□, (column address strobe request signal) output from refresh control block 14.]
OR gate 156 outputs τ (column address strobe signal) and RAS□ output from Nant gate 155. Tori fresh control block 14
RAS□ output from.

(Row address strobe request signal)
It is composed of an OR gate 157 which outputs RAS6 (row address strobe signal).

In the above configuration, each signal is output at the timing shown in FIG. A timing signal T'+tw is output in synchronization with the internal clock, and the cycle changes every time this T□ is output. Further, RAS and CAS strobe signals are applied to the memory block 16 in synchronization with the timing signals Teas and TCA3 outputted from the timing block 12, and refreshing is performed. The memory address is changed to M by the multiplexer 153 when
RA is output in the order of row address - column address,
At the time of writing, MWA is output in the same way, and each is output to the memory block as MA. The write enable (WE) signal for the memory block 16 is generated when the ■ flag output from the address generation block 11 and the bank select signal (WBS) are output at the same time, making the memory block 16 ready for writing. .

In the above embodiment, one of the device W (A) 20 and the device (B) 30 performs reading while the other performs writing, but both devices may perform writing or reading operations at the same time. Yes, it is possible (in this case, it is necessary to perform weighting to give priority to either writing or reading).

Furthermore, in the present invention, assuming that writing and reading are performed so that the banks of read addresses and write addresses are always different, the read/write cycle period is set to R.
The period may be set to be less than or equal to the shorter of the CLK period and the WCLK period. However, if this is not possible (e.g. RCL
(When the cycle of K or WCLK must be shortened, or when writing and continuous writing in the same bank occur)
etc., the circuit may be configured so that it can only write/read multiple bytes.

An example of this is shown in Figure 5, where WCLK and WPA
Clock signal for writing based on GE (WCLK2)
Flip-flops 201 and 202 that generate WD
Write ATA to the HN area of the memory 205 in synchronization with WCLK2 register 203, write WDATA to the LSI area of the memory 205 in synchronization with the output signal of the flip-flop 201, and write the data from the register 204 and register 203 H6J It consists of a memory 205 having an area and an area in which data from the register 204 is written.

In the configuration of FIG. 5, write data WDATA is WC
Each time LK is input, registers 203 and 204 alternately perform a write operation, and two write operations are performed simultaneously to memory 205.
Bytes are written.

〔Effect of the invention〕

As explained above, according to the image data recording device of the present invention, the write memory area and the read memory area are set based on control information output from a plurality of devices, and when a predetermined condition is met, image data is recorded. Since writing and continuous writing are performed simultaneously, simultaneous reading and writing can be performed efficiently and at high speed with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing details of the address generation block in FIG. 1, and FIG. 3 is a main part of the memory control block 15 in FIG. 1. FIG. 4 is a time chart showing the operation of each part of an embodiment of the present invention, and FIG. 5 is a circuit diagram showing main parts of another embodiment of the present invention. Explanation of symbols 11...Address generation block, 12...Timing block, 13...Write data register, 14...Refresh control block, 15...Memory control block, 16...Memory block , 17... Read data register, 20-... Device (A), 30... Device (B), 101...
Read address counter, 102, 107...decoder, 103, 108.153...multiplexer, 104
, 105.109.113...Flip-flop, 1
06...Write address counter, 111...Comparator, 112, 152.154.155...Nant gate,
151, 156.157... or gate, 201, 2
02...Flip-flop, 203, 204...Register, 205...Memory. Patent applicant Fuji Xerox Co., Ltd. Agent
Patent Attorney Shin Matsubara 2 Same as Seiji Muraki Same as Same as Same as Same as Jun Ueshima- Same as same as Hiroaki Sakai p clock included in Figure 2 TRW Cycle RAW
II/-Haruma Figure 4 Figure 5

Claims (4)

[Claims] (1) In an image data recording device that writes image data output from a certain device into a memory and performs relay processing to read the written data to another device, data from the output device is stored. a memory block having a first memory area and a second memory area for reading data to the input device; 1st
. An image data recording apparatus, characterized in that it is provided with a control means for setting a second memory area and simultaneously executing writing and reading processes for the second memory area. (2) The image data recording device according to claim 1, wherein the control information includes write and read page information and a clock signal. (3) When the write clock signal and the read clock signal as the control information are generated within the same processing cycle, and the first memory area and the second memory area are in the same bank, 2. The image data recording apparatus according to claim 1, further comprising a control means for performing processing from either writing or reading according to a set priority order. (4) A memory write address or a memory read address for the memory block is generated by counting the clock signals generated within a period during which the page information is output. The image data recording device according to items 1 and 3.