JPS5694469A - Pipeline processing device provided with linkage bus - Google Patents

Pipeline processing device provided with linkage bus

Info

Publication number
JPS5694469A
JPS5694469A JP17367979A JP17367979A JPS5694469A JP S5694469 A JPS5694469 A JP S5694469A JP 17367979 A JP17367979 A JP 17367979A JP 17367979 A JP17367979 A JP 17367979A JP S5694469 A JPS5694469 A JP S5694469A
Authority
JP
Japan
Prior art keywords
data
register
successively
processing device
device provided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17367979A
Other languages
Japanese (ja)
Inventor
Satoru Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17367979A priority Critical patent/JPS5694469A/en
Publication of JPS5694469A publication Critical patent/JPS5694469A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To separate the processing where operated resultant element data is stored in the vector register and the processing where the same data is utilized for the next processing from each other, by providing a linkage bus. CONSTITUTION:Element data a0 and b0, a1 and b1,... are read from vector registers 1-0 and 1-1 successively, and data a0-an are set to input register 7-0 successively, and data b0-bn are set to input register 7-1 successively. These data a0-an and b0-bn are operated successively by pipeline adding part 3, and operated resultant element data c0-cn are set to register 13. Next, element data d0, d1,... are read from vector register 1-3 and are set to register 7-1 successively, and simultaneously, data c0, c1,... are set to register 7-0 successively through linkage bus 5. Simultaneously, data c0-cn are set to vector register 1-2 also through operation result storage bus line 4.
JP17367979A 1979-12-27 1979-12-27 Pipeline processing device provided with linkage bus Pending JPS5694469A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17367979A JPS5694469A (en) 1979-12-27 1979-12-27 Pipeline processing device provided with linkage bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17367979A JPS5694469A (en) 1979-12-27 1979-12-27 Pipeline processing device provided with linkage bus

Publications (1)

Publication Number Publication Date
JPS5694469A true JPS5694469A (en) 1981-07-30

Family

ID=15965082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17367979A Pending JPS5694469A (en) 1979-12-27 1979-12-27 Pipeline processing device provided with linkage bus

Country Status (1)

Country Link
JP (1) JPS5694469A (en)

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