JPS5688562A - Control system for parallel execution of linked instruction - Google Patents

Control system for parallel execution of linked instruction

Info

Publication number
JPS5688562A
JPS5688562A JP16663779A JP16663779A JPS5688562A JP S5688562 A JPS5688562 A JP S5688562A JP 16663779 A JP16663779 A JP 16663779A JP 16663779 A JP16663779 A JP 16663779A JP S5688562 A JPS5688562 A JP S5688562A
Authority
JP
Japan
Prior art keywords
element data
mutually
linked
instructions
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16663779A
Other languages
Japanese (ja)
Other versions
JPS6042985B2 (en
Inventor
Tetsuo Okamoto
Masanori Mogi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16663779A priority Critical patent/JPS6042985B2/en
Publication of JPS5688562A publication Critical patent/JPS5688562A/en
Publication of JPS6042985B2 publication Critical patent/JPS6042985B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To increase a processing speed by executing linked instruction in parallel by shifting the bank access timing for fetching current element data successively corresponding to the next instruction. CONSTITUTION:So that mutually continuous addresses in vector registers #0VR, #VR... will be positioned at mutually different banks 2-0...2-3, (m) units of vector registers are composed of memory device 1 interleaved into a k-bank memory. On the other hand, the bank access timing for storing sucessively element data X1, X2... of processing results by mutually linked instructions is mutually shifted from that for fetching successively current element data X1, X2... corresponding to the next instructions providing arithmetic by using the element data of the processing results. Consequently, the processing speed is increased by executing linked instructions in parallel only by giving latent time of only several cycles.
JP16663779A 1979-12-21 1979-12-21 Parallel execution control method for linked instructions Expired JPS6042985B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16663779A JPS6042985B2 (en) 1979-12-21 1979-12-21 Parallel execution control method for linked instructions

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16663779A JPS6042985B2 (en) 1979-12-21 1979-12-21 Parallel execution control method for linked instructions

Publications (2)

Publication Number Publication Date
JPS5688562A true JPS5688562A (en) 1981-07-18
JPS6042985B2 JPS6042985B2 (en) 1985-09-26

Family

ID=15834966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16663779A Expired JPS6042985B2 (en) 1979-12-21 1979-12-21 Parallel execution control method for linked instructions

Country Status (1)

Country Link
JP (1) JPS6042985B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0367995A2 (en) * 1988-10-08 1990-05-16 Nec Corporation Vector data transfer controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0367995A2 (en) * 1988-10-08 1990-05-16 Nec Corporation Vector data transfer controller

Also Published As

Publication number Publication date
JPS6042985B2 (en) 1985-09-26

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