JPS55131850A - Microprogram controller - Google Patents

Microprogram controller

Info

Publication number
JPS55131850A
JPS55131850A JP3931379A JP3931379A JPS55131850A JP S55131850 A JPS55131850 A JP S55131850A JP 3931379 A JP3931379 A JP 3931379A JP 3931379 A JP3931379 A JP 3931379A JP S55131850 A JPS55131850 A JP S55131850A
Authority
JP
Japan
Prior art keywords
control
cycles
read
arithmetic part
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3931379A
Other languages
Japanese (ja)
Inventor
Takashi Nishizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3931379A priority Critical patent/JPS55131850A/en
Publication of JPS55131850A publication Critical patent/JPS55131850A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To remove a restriction on the control function of a main control part by previously storing instructions, read from a control memory, in a register bank which provides a high-speed read, by reading them at need by an instruction, and by exercising high-speed control over an auxiliary arithmetic part in a basic cycle.
CONSTITUTION: Arithmetic part 6 composed of main arithmetic part 6a operating at basic cycles under the control of a microprogram and auxiliary arithmetic part 6b operating at cylces obtained by the basic cycles by an integer, and control register 5 which reads microinstructions from control memory 1 synchronizing with cycles for the storage of microinstructions and operation of arithmetic part 6 are provided. Additionally, register bank 7 is provided which consists of registers stored with fields of some of microinstrctions read and sent to register 5 and reading fields of some of microinstructions at cycles obtained by the basis cycles by the integer, and some of micro-instructions read out from control memory 1 are stored in bank 7 and read as needed so as to exercise high-speed control over arithemetic part 6b, thereby removing a restriction on the control function of control part 6a.
COPYRIGHT: (C)1980,JPO&Japio
JP3931379A 1979-04-03 1979-04-03 Microprogram controller Pending JPS55131850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3931379A JPS55131850A (en) 1979-04-03 1979-04-03 Microprogram controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3931379A JPS55131850A (en) 1979-04-03 1979-04-03 Microprogram controller

Publications (1)

Publication Number Publication Date
JPS55131850A true JPS55131850A (en) 1980-10-14

Family

ID=12549614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3931379A Pending JPS55131850A (en) 1979-04-03 1979-04-03 Microprogram controller

Country Status (1)

Country Link
JP (1) JPS55131850A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5916050A (en) * 1982-07-16 1984-01-27 Nec Corp Dynamic gate array

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5916050A (en) * 1982-07-16 1984-01-27 Nec Corp Dynamic gate array
JPH0230056B2 (en) * 1982-07-16 1990-07-04 Nippon Electric Co

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