JPS5533234A - Program reconfiguration system of sequential controller - Google Patents

Program reconfiguration system of sequential controller

Info

Publication number
JPS5533234A
JPS5533234A JP10596078A JP10596078A JPS5533234A JP S5533234 A JPS5533234 A JP S5533234A JP 10596078 A JP10596078 A JP 10596078A JP 10596078 A JP10596078 A JP 10596078A JP S5533234 A JPS5533234 A JP S5533234A
Authority
JP
Japan
Prior art keywords
program
instruction
state
memory part
arithmetic control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10596078A
Other languages
Japanese (ja)
Other versions
JPS607801B2 (en
Inventor
Tatsuo Otsu
Kazuo Mushishika
Hisao Toyama
Minoru Oka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP10596078A priority Critical patent/JPS607801B2/en
Publication of JPS5533234A publication Critical patent/JPS5533234A/en
Publication of JPS607801B2 publication Critical patent/JPS607801B2/en
Expired legal-status Critical Current

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  • Programmable Controllers (AREA)

Abstract

PURPOSE: To simplify the partial modification of a program by regarding a series of instruction, relating with each circuit block divided by functions, as an instruction group.
CONSTITUTION: A group of instructions, where each circuit element of the circuit constitution in the virtual sequence figure is expressed as one instruction, are stored in program memory part 3. Instructions stored in program memory part 3 are sequentially read out by arithmetic control part 4. On the basis of an instruction fetched from memory part 3, arithmetic control part 4 performs logical operation as to the logical state of each input line obtained from input fetch part 1 and the output control state at that time so as to decide on a new output control state. In this state, desired sequence operation is realized. Program console part B consists of arithmetic control part 7, memory part 8, input unit 9, output unit 10, and interfaces 6 and 11.
COPYRIGHT: (C)1980,JPO&Japio
JP10596078A 1978-08-30 1978-08-30 Sequence controller device Expired JPS607801B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10596078A JPS607801B2 (en) 1978-08-30 1978-08-30 Sequence controller device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10596078A JPS607801B2 (en) 1978-08-30 1978-08-30 Sequence controller device

Publications (2)

Publication Number Publication Date
JPS5533234A true JPS5533234A (en) 1980-03-08
JPS607801B2 JPS607801B2 (en) 1985-02-27

Family

ID=14421362

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10596078A Expired JPS607801B2 (en) 1978-08-30 1978-08-30 Sequence controller device

Country Status (1)

Country Link
JP (1) JPS607801B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0315043Y2 (en) * 1985-01-21 1991-04-03
JPH045127Y2 (en) * 1988-03-24 1992-02-14

Also Published As

Publication number Publication date
JPS607801B2 (en) 1985-02-27

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