JPS5448446A - Memory unit control system - Google Patents

Memory unit control system

Info

Publication number
JPS5448446A
JPS5448446A JP8158277A JP8158277A JPS5448446A JP S5448446 A JPS5448446 A JP S5448446A JP 8158277 A JP8158277 A JP 8158277A JP 8158277 A JP8158277 A JP 8158277A JP S5448446 A JPS5448446 A JP S5448446A
Authority
JP
Japan
Prior art keywords
memory
speed
different
digit location
mmd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8158277A
Other languages
Japanese (ja)
Other versions
JPS5821735B2 (en
Inventor
Hiroshi Shintani
Kazuo Ishida
Yoshio Sakurai
Tetsuo Urushibara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP52081582A priority Critical patent/JPS5821735B2/en
Publication of JPS5448446A publication Critical patent/JPS5448446A/en
Publication of JPS5821735B2 publication Critical patent/JPS5821735B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)

Abstract

PURPOSE:To enable the control of memory different in speed and to simplify the unit, by using shift registers, in the information processing system including a plurality of memory devices different in speed. CONSTITUTION:In the information processing system including the processor interpreting and executing the program stored in the memory devices MMa to MMd which are different in speed and the memory control cirucit external the processor or internal it, the memory unit control circuit is provided with shift registers 19 shifting toward 1 at all times. Further, at the initiation of access of the memory units, the digit location set section inputting the memory access initiation information to the digit location for different registers corresponding to the speed of the memory units MMa to MMd is constituted, and the short circuits 7a to 7d selecting and shortening the digit location and the memory start signal forming circuit 3 and AND circuits 12, 14 to 17 are provided.
JP52081582A 1977-07-08 1977-07-08 Memory device control method Expired JPS5821735B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52081582A JPS5821735B2 (en) 1977-07-08 1977-07-08 Memory device control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52081582A JPS5821735B2 (en) 1977-07-08 1977-07-08 Memory device control method

Publications (2)

Publication Number Publication Date
JPS5448446A true JPS5448446A (en) 1979-04-17
JPS5821735B2 JPS5821735B2 (en) 1983-05-02

Family

ID=13750302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52081582A Expired JPS5821735B2 (en) 1977-07-08 1977-07-08 Memory device control method

Country Status (1)

Country Link
JP (1) JPS5821735B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63140353A (en) * 1986-12-02 1988-06-11 Nec Corp Main memory access control system
US5194943A (en) * 1990-11-06 1993-03-16 Hitachi, Ltd. Video camera having a γ-correction circuit for correcting level characteristics of a luminance signal included in a video signal

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01117439U (en) * 1988-01-27 1989-08-08

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4917938A (en) * 1972-04-06 1974-02-16
JPS5235946A (en) * 1975-09-16 1977-03-18 Hitachi Ltd Memory control unit
JPS5247330A (en) * 1975-10-13 1977-04-15 Fujitsu Ltd Storage control system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4917938A (en) * 1972-04-06 1974-02-16
JPS5235946A (en) * 1975-09-16 1977-03-18 Hitachi Ltd Memory control unit
JPS5247330A (en) * 1975-10-13 1977-04-15 Fujitsu Ltd Storage control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63140353A (en) * 1986-12-02 1988-06-11 Nec Corp Main memory access control system
US5194943A (en) * 1990-11-06 1993-03-16 Hitachi, Ltd. Video camera having a γ-correction circuit for correcting level characteristics of a luminance signal included in a video signal

Also Published As

Publication number Publication date
JPS5821735B2 (en) 1983-05-02

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