JPS5491031A - Timing controller - Google Patents

Timing controller

Info

Publication number
JPS5491031A
JPS5491031A JP15797177A JP15797177A JPS5491031A JP S5491031 A JPS5491031 A JP S5491031A JP 15797177 A JP15797177 A JP 15797177A JP 15797177 A JP15797177 A JP 15797177A JP S5491031 A JPS5491031 A JP S5491031A
Authority
JP
Japan
Prior art keywords
counter
cpu1
program
memory part
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15797177A
Other languages
Japanese (ja)
Inventor
Teruo Tsukamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15797177A priority Critical patent/JPS5491031A/en
Publication of JPS5491031A publication Critical patent/JPS5491031A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To make it possible to update a program without laying a load upon the program by modifying the structure of the program at its minimum in a controller for a transaction memory provided to the memory unit of an electronic switchboard.
CONSTITUTION: Both CPU1 and timing controller 2 are provided, and this controller 2 is equipped with timer memory part 21 stored with a timer value and mask number sent out from CPU1 and counter 22 updated by a fixed input clock signal; access to memory part 21 is made by timer address information assigned depending upon the contents of counter 22 when the contents of the fixed bit of this counter 22 are "0", and writing from CPU1 to memory part 21 is made possible when the fixed bit of counter 22 is "1". Further, arithmetic circuit part 23 is provided which updates the timer value read out from memory part 21 according to address information indicated by counter 22 and outputs address infomation and the mask number by detecting an overflow judging from the update result, and information circuit 24 to which the address information and task number are both registered is also provided.
COPYRIGHT: (C)1979,JPO&Japio
JP15797177A 1977-12-28 1977-12-28 Timing controller Pending JPS5491031A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15797177A JPS5491031A (en) 1977-12-28 1977-12-28 Timing controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15797177A JPS5491031A (en) 1977-12-28 1977-12-28 Timing controller

Publications (1)

Publication Number Publication Date
JPS5491031A true JPS5491031A (en) 1979-07-19

Family

ID=15661429

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15797177A Pending JPS5491031A (en) 1977-12-28 1977-12-28 Timing controller

Country Status (1)

Country Link
JP (1) JPS5491031A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62212842A (en) * 1986-03-14 1987-09-18 Nec Corp Virtual process timer system for information processing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62212842A (en) * 1986-03-14 1987-09-18 Nec Corp Virtual process timer system for information processing system

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