JPS5699559A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS5699559A
JPS5699559A JP86380A JP86380A JPS5699559A JP S5699559 A JPS5699559 A JP S5699559A JP 86380 A JP86380 A JP 86380A JP 86380 A JP86380 A JP 86380A JP S5699559 A JPS5699559 A JP S5699559A
Authority
JP
Japan
Prior art keywords
period
memory
control
instruction
during
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP86380A
Other languages
Japanese (ja)
Inventor
Yukio Nakamura
Shigeki Yamada
Hideo Yamauchi
Yoshio Inui
Hiroshi Fujita
Akio Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP86380A priority Critical patent/JPS5699559A/en
Publication of JPS5699559A publication Critical patent/JPS5699559A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Abstract

PURPOSE:To realize an economical load distribution type multiprocessor system, by making it possible that respective control devices use the program memory provided commonly in time division. CONSTITUTION:Control processing device 11 executes one instruction during the time from the start of the control clock period to, for example, the 3/4 period and outputs the memory address of program memory 200 to address line 31 during the rest 1/4 period. Selector circuit 300 selects address line 31 during the said 1/4 period and inputs address information to memory 200. The instruction output to output line 401 of memory 200 is distributed to device 11 by distributing circuit 400. Device 11 sets this instruction in itself and executes it at the next period. Other control devices 12-14 are operated similarly by control clocks PC2-PC4 whose phase is shifted successively from the phase of control clock PC1 of device 11 by every 1/4 period. As a result, memory 200 is used time-divisionally.
JP86380A 1980-01-10 1980-01-10 Memory control system Pending JPS5699559A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP86380A JPS5699559A (en) 1980-01-10 1980-01-10 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP86380A JPS5699559A (en) 1980-01-10 1980-01-10 Memory control system

Publications (1)

Publication Number Publication Date
JPS5699559A true JPS5699559A (en) 1981-08-10

Family

ID=11485497

Family Applications (1)

Application Number Title Priority Date Filing Date
JP86380A Pending JPS5699559A (en) 1980-01-10 1980-01-10 Memory control system

Country Status (1)

Country Link
JP (1) JPS5699559A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5744311A (en) * 1980-06-26 1982-03-12 Rca Corp Television intermediate frequendy amplifier
WO2009118776A1 (en) 2008-03-25 2009-10-01 富士通株式会社 Multiprocessor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5744311A (en) * 1980-06-26 1982-03-12 Rca Corp Television intermediate frequendy amplifier
JPS6335122B2 (en) * 1980-06-26 1988-07-13 Rca Corp
WO2009118776A1 (en) 2008-03-25 2009-10-01 富士通株式会社 Multiprocessor

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