JPS5668878A - Data processor - Google Patents

Data processor

Info

Publication number
JPS5668878A
JPS5668878A JP14515379A JP14515379A JPS5668878A JP S5668878 A JPS5668878 A JP S5668878A JP 14515379 A JP14515379 A JP 14515379A JP 14515379 A JP14515379 A JP 14515379A JP S5668878 A JPS5668878 A JP S5668878A
Authority
JP
Japan
Prior art keywords
instruction
micro
instructions
register
micro instructions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14515379A
Other languages
Japanese (ja)
Inventor
Hiromi Nanba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14515379A priority Critical patent/JPS5668878A/en
Publication of JPS5668878A publication Critical patent/JPS5668878A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To store micro instruction and another micro instructions different in level from said micro instructions in the same memory, by deciding whether the read instruction is a lower instruction or a higher instruction and by executing the lower instruction in case of a higher instruction and by executing the instruction directly in acse of a lower instruction, in respect to the use of them.
CONSTITUTION: Micro instructions and micro instructions A different in level from said micro instructions are stored in main memory 1 and are read by program counter 2 and are loaded into instruction register 6. It is decided by mapping PROM 9 whether the instruction on this register 6 is a micro instruction of micro instruction A, and decision signal 24 is output. In case of a micro instruction, the instruction code is converted to the execution start address of micro instruction B by PROM9 and is given to sequnce contrller 10, and micro instruction B is executed by registers, ALU15, and so on. If the instruction on register 6 is micro instruction A, the instruction is developed to the same format as micro instruction B by code convert part 8 and is executed as it is.
COPYRIGHT: (C)1981,JPO&Japio
JP14515379A 1979-11-09 1979-11-09 Data processor Pending JPS5668878A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14515379A JPS5668878A (en) 1979-11-09 1979-11-09 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14515379A JPS5668878A (en) 1979-11-09 1979-11-09 Data processor

Publications (1)

Publication Number Publication Date
JPS5668878A true JPS5668878A (en) 1981-06-09

Family

ID=15378640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14515379A Pending JPS5668878A (en) 1979-11-09 1979-11-09 Data processor

Country Status (1)

Country Link
JP (1) JPS5668878A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0279953A2 (en) * 1987-02-24 1988-08-31 Texas Instruments Incorporated Computer system having mixed macrocode and microcode instruction execution
US5235686A (en) * 1987-02-24 1993-08-10 Texas Instruments Incorporated Computer system having mixed macrocode and microcode

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0279953A2 (en) * 1987-02-24 1988-08-31 Texas Instruments Incorporated Computer system having mixed macrocode and microcode instruction execution
US5235686A (en) * 1987-02-24 1993-08-10 Texas Instruments Incorporated Computer system having mixed macrocode and microcode

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