JPS6042985B2 - Parallel execution control method for linked instructions - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for controlling the parallel execution of linked instructions, particularly in a processing system that performs vector operations. A part of the vector register is located in each bank, and each bank has an input/output section separated from the others, and furthermore, the vector register is constituted by a memory, and mutual communication within one vector register is provided. Bank access timing for sequentially storing element data X, X2, X3, etc. of operations of linked instructions by interleaving so that consecutive addresses are located in different banks; In response to the next instruction, the element data x, , X2, X3...
Bank access to sequentially fetch...
This invention relates to a parallel execution control system for linked instructions in which the timings are shifted from each other.

In vector arithmetic processing, generally element data belonging to vector B bl, b29b3...
・And/or calculate element data Cl, C2, Cs, etc. belonging to vector C to obtain element data a, , a.

, aa..., and obtain the element data a.
1, a29a3, . . . are stored as element data belonging to vector A. Such arithmetic processing is performed for each element a,,a. ,a.・・・・・・
. However, as shown in Figure 1,
Multiple instructions are linked such that a first load instruction VL loads #1 vector register #1VR, and then a second add instruction VA immediately following uses the contents of #1 vector register #1VR. In this case, as shown in FIG. 2, the execution of the instruction VA is usually started after the loading by the instruction VL is completed, resulting in a decrease in processing efficiency.

For this purpose, as shown in FIG. 3, element data

, Xl, X2... are loaded and stored in order in the #1 vector register,
It is considered that the data is branched and also fetched for the second instruction (2)A, and the instruction VA is executed in parallel from the middle of the execution of the instruction (2)L. In the case of the method shown in FIG. 3, the element data X is immediately loaded when the loading of the element data formula is completed. It has the excellent advantage of being able to start calculations regarding the next instruction ``A'' using . but,
As mentioned above, a bus is required for branching and fetching data. The present invention enables the empty state of the #1 vector register to be obtained at an early point after the loading of element data is completed as shown in FIG. 4 without creating the above-mentioned bus. The purpose is to enable processing related to VA to be started.

Therefore, the parallel execution control method for linked instructions of the present invention is provided with m vector registers and a plurality of element data Bi, b2, b3, etc. belonging to vector B for the m vector registers. In a vector arithmetic processing system having a function of retrieving and/or storing ..., the m (m〉2) vectors are arranged such that consecutive addresses in the vector register are located in different banks.・Click the register to K. (k>2)
It is composed of storage devices interleaved with bank memories, and each bank of the storage device has its input/output section separated for each bank, and data from a plurality of vector data storage sources can be received for each bank. By individually inputting data to each bank via an input multiplexer, and outputting data to multiple vector data points through an output multiplexer provided for each cutting point,
It is configured so that accesses to different banks can be started from the same point in time, and element data Xl, X2, X3, etc. are processed as a result of mutually linked instructions.
Bank access timing for sequentially storing ... and element data Xl, X2 of the above processing results
, j..., corresponding element data Xl, X2, X3...
This feature is characterized in that the bank access timing for sequentially fetching the data is shifted from each other.
This will be explained below with reference to the drawings. FIG. 5 shows the configuration of an embodiment of the present invention.

In the figure, numeral 1 is a storage device that constitutes a vector register, #0■R, #1VR, ... #15VR are vector registers, 2, -0, 2-1, 2-2, 2- 3 are banks, 3-0 to 3-2 and 4-0 to 4, respectively.
-4 is a buffer register provided as needed, 5 is an adder, 6 is a multiplier, 7 is a buffer for loading element data, 8 is a buffer for storing element data, 9 or 25 each represent a multiplexer. In the case shown, each vector ● register #
0■R, #1VR, .
Address ROlr4. of register #0■R, #1VR,...
, l8J... is in bank 2-0, address Rljr
5J... is in bank 2-1, address R2. , r6yo・
...is in bank 2-2, addresses R3J, r7J...
.

However, interleaving in general storage devices is designed to enable successive fetching of a series of data. However, in the case of the present invention, the above-mentioned interleaving structure is taken into consideration in order to efficiently execute the linked instructions as shown in FIG. They differ significantly in that they may be accessed in parallel under timing. It may be considered that the buffer registers 3-0 to 3-2 and 4-0 to 4-4 shown in FIG. 5 are used to provide a holding state for one cycle, for example, as necessary.

When executing commands ``L'' and ``A'' as shown in FIG. 1, the following processing is performed.

(1) Timing T in #1 vector register #1■R
Element ●Data X in O and Tl, respectively.

, Xl are stored in order, and bank 2-2 is accessed to store element data X2. This timing is defined as T2. (2) This timing T2
At , bank 2-1 is accessed and element data y1 is read from #2 vector register #2VR.

Also, at timing T2, element data Y of #2 vector register #2VR, which was read by accessing bank 2-0 at timing T1. is set in the illustrated register 4-0, for example. Then, again at the above timing T2, bank 2-0 is accessed and element data X is stored first from #1 vector register #1VR. is read out. (3) Then, at timing T2, the element data read from bank 2-0 and the contents of illustrated register 4-0 (element ● data YO) are combined by adder 5 (Y
O+XO) addition processing is started.

(4) Next, at timing T3, the loaded element data! is stored in #1 vector register #1VR by accessing bank 2-3, element data Y2 is read from bank 2-2, element data y1 exists in register 4-0, and Elements stored from 1 to data X
1 is read.

That is, the addition process of (y1+X1) is started. (5)
Assuming that the time required for addition by the adder 5 is one cycle, the result of (YO+XO) is output at the above timing T3, and by accessing bank 2-0, the contents are transferred to #3 vector ● register # It will be stored at address RO of 3VR.

In the above case, the element data loaded by instruction R is stored in the vector register, then read out two cycles later, and used for the operation by instruction A. .

However, it goes without saying that the number of cycles after which the data is read and processed may vary depending on the time required for processing by the adder and the number of banks. However, the processing speed is significantly improved compared to the processing shown in FIG. As described above, according to the present invention, it is possible to execute linked instructions in parallel by giving them at most several cycles of time.

[Brief explanation of drawings]

1 to 3 are explanatory diagrams for explaining the prerequisite problems of the present invention, FIG. 4 is an explanatory diagram for explaining the present invention in detail, and FIG. 5 shows the configuration of an embodiment of the present invention.

Claims (1)

[Claims] 1 A vector that is equipped with m vector registers and has the function of extracting and/or storing a plurality of element data b_1, b_2, b_3, etc. belonging to vector B into the m vector registers. In the arithmetic processing system, the m (m>2) vector registers are arranged so that consecutive addresses in the vector registers are located in different banks.
It is composed of storage devices interleaved with bank memories, and each bank of the storage device has its input/output section separated for each bank, and data from a plurality of vector data storage sources can be received for each bank. By inputting data to each bank individually through an input multiplexer and outputting data to a vector data output destination through a multiplexer provided for each output destination, access to different banks can be started from the same point. Element data x_1, x_2, x_3, etc. as a result of processing by mutually linked instructions
Bank access timing for sequentially storing . . . and element data x_1, x_2 of the above processing results
, x_3..., corresponding element data x_1, x_2, x_3.
A method for controlling parallel execution of linked instructions, characterized in that bank access timings for sequentially fetching . . . are staggered.