JPS5797169A - Vector data processing device - Google Patents

Abstract

PURPOSE:To transmit an instruction to an operator by a simple control, by constituting a vector register consisting of plural elements, of plural banks each. CONSTITUTION:A bank timing shift register 22 is operated in order to prescribe a bank timing, and its contents are shifted to the right at every 1 cycle. When a flip-flop (a) is logical ''1'', the bank timing is made A, and when a flip-flop (b) is logical ''1'', the bank timing becomes B. An adder using timing storage part 24 stores a bank timing used for access of #0 element by an adder 10, and a multiplier using timing storage part 25 stores a bank timig used for access of #0 element by a multiplier 11. When a vector instruction is received, an instruction control part 8 detects an idle bank timing, and informs to the processing pipe line concerned that the instruction should be executed by use of said idle bank timing.