JPS56129955A - Data processor - Google Patents
Data processorInfo
- Publication number
- JPS56129955A JPS56129955A JP3218480A JP3218480A JPS56129955A JP S56129955 A JPS56129955 A JP S56129955A JP 3218480 A JP3218480 A JP 3218480A JP 3218480 A JP3218480 A JP 3218480A JP S56129955 A JPS56129955 A JP S56129955A
- Authority
- JP
- Japan
- Prior art keywords
- data processing
- result
- address adder
- register
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1695—Error detection or correction of the data by redundancy in hardware which are operating with time diversity
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
Abstract
PURPOSE:To reduce the number of data processing circuits and to increase the processing speed, by using the same data processing with shifted timing to similar data processings, in duplicated data processors. CONSTITUTION:In the normal operation in which the operand is not in variable length, the address adders 7, 9 make the same operation at the same time, and the result is compared at a comparison circuit 11. In case the operand is in variable length, the 1st data processing S is made at the address adder 7 in the timing T1, and the 2nd data processing S+L is made at the address adder 9, the result of processing is stored to the register 8 at the address adder 7 and the result of processing at the address adder 9 is stored in the register 10. The data processing S+L is made at the address adder 7 in the next timing T2, and the data processing S is made for the result and the content of the register 10 at the address adder 9, and the result and the content of the register 8 are respectvely compared.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55032184A JPS6051137B2 (en) | 1980-03-14 | 1980-03-14 | data processing equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55032184A JPS6051137B2 (en) | 1980-03-14 | 1980-03-14 | data processing equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56129955A true JPS56129955A (en) | 1981-10-12 |
JPS6051137B2 JPS6051137B2 (en) | 1985-11-12 |
Family
ID=12351825
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55032184A Expired JPS6051137B2 (en) | 1980-03-14 | 1980-03-14 | data processing equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6051137B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5794843A (en) * | 1980-12-05 | 1982-06-12 | Nec Corp | Arithmetic device |
-
1980
- 1980-03-14 JP JP55032184A patent/JPS6051137B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5794843A (en) * | 1980-12-05 | 1982-06-12 | Nec Corp | Arithmetic device |
Also Published As
Publication number | Publication date |
---|---|
JPS6051137B2 (en) | 1985-11-12 |
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