JPH05158968A - Instruction issue control device - Google Patents

Abstract

PURPOSE:To speed up vector processing by minimizing a queue time without allowing reading data to exceed writing data when a writing instruction and a reading instruction are successively continued in this order in the same entry of a memory for storing vector data. CONSTITUTION:The using entry number of the preceding writing instruction is stored in an entry storing circuit 21 and compared with the using entery number (stored in a register 17) of the succeeding reading instruction by a comparator 23. When both the numbers are equal to each other, a reading control circuit 14 detects the arrival of an idle slot other than the using slot of the writing instruction after the lapse of a prescribed time determined by the execution time of the writing instruction and then issues the reading instruction. When both the numbers are not equal, the reading instruction is issued immediately after the arrival of an idle slot.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction issue control device for a vector processing device, and more particularly to a write / read instruction issue control device for a vector processing device having a vector data unit composed of a RAM.

[0002]

2. Description of the Related Art The significance of the existence of a vector processing device lies in the fact that a large amount of data is processed at high speed by vector operation. In order to realize high-speed processing, various measures are taken in the vector operation itself, but one of the means is to reduce the access circuit to the memory for referring to the operation data and storing the operation result. .. Therefore, it is common practice to have a vector data unit in the vector processing device for storing an intermediate result of an operation which is referred to by a subsequent vector instruction.

If the capacity of the vector data unit is large, the number of entries of the vector data that can be stored is increased and the access to the memory can be reduced more. Therefore, a large capacity RAM is often used for the vector data unit. However, as a general limitation of RAM, there are cases in which the same read / write minimum unit cannot perform write and read operations at the same time.

When the RAM is used in a device such as a vector data unit of a vector processing device for reading or writing a plurality of continuous data and requiring a plurality of instructions to operate in parallel, there are the above-mentioned restrictions. Therefore, in general, as shown in FIG. 2, the physical configuration unit VD of RAM is
Logical unit of M0 to VDM3 and data unit VD0 to VD1
(Element numbers in parentheses) and the physical unit
In VDM0 to VDM3, processing is performed in a time-sharing manner, and processing is shifted by one processing time for each physical configuration unit time. At this time, the number of physical constitutional units (“4” in FIG. 2) is the number of time divisions, which is the number of processes that can logically operate simultaneously. The time-divided one processing time unit is called a slot.

FIG. 3 is a time chart of the operation in the vector data unit constructed as shown in FIG. Write operation to VD0 in slot 0, in slot 2
The read operation is executed from VD1. Note that W indicates writing and R indicates reading.

In each physical unit, write and read operations are performed at the indicated slot timing, the processing timing is shifted between physical units, and the logical data structure is arranged beyond the physical unit. Therefore, the write and read operations can be performed continuously and can be performed simultaneously.

Further, in the vector arithmetic processing device, the time (PRE
PROCESS TIME, PPT (hereinafter described) is constant, but operation execution time (FUNCTION UNIT TIME, FUT, described below)
Often differs depending on the calculation to be processed.

When the arithmetic instruction to be executed is an instruction to store the result in the vector data unit, the timing at which the data arrives at the vector data unit due to this FUT is different, so that the arithmetic unit and the arithmetic unit are used for adjusting the timing with the write slot timing. It has a timing adjustment buffer with the same number of slots as the vector data unit, and when issuing a vector data unit write command,
It is often used to specify only the slot to be used without regard to the timing of writing and to issue the subsequent instruction earlier.

FIG. 4 is a simplified block diagram of a vector processing device including a vector data unit to which the above-mentioned buffer is connected and a vector calculator. In the figure, the vector data unit 50 has the configuration shown in FIG.
It has four RAMs M0 to VDM3, and further has a buffer 53 for timing adjustment as described above. In this example, since there are two access paths to the RAM in the vector data unit 50, the timing adjustment buffer 53 is provided for each path.

52 is a vector operand register,
Reference numeral 54 is a vector calculator, and 55 is a crossbar.

In the instruction issue control device for issuing an instruction to the vector processing device as described above, in the prior art, when the preceding vector data unit write command is followed by the vector data unit read command,
If the entries of the vector data units used by each other are not the same, the slot is checked for issuance, and if the entries match, the read will precede depending on the timing of issue even if the slot is free. there is a possibility. Therefore, it is controlled so that the subsequent read command is not issued until the preceding write command is completed.

When issuing a command to the vector processing device having the vector data unit composed of the RAM as described above, the conventional command issuing control device uses the write command to the preceding vector data unit and the subsequent read command. When the entries of the vector data unit match, in order to guarantee the processing order for the vector data unit, the issuance of the subsequent read instruction is suppressed until the processing of the preceding write instruction is completed. Therefore, a program including a large number of such instruction sequences has a drawback that the overall processing execution time becomes long.

[0013]

It is an object of the present invention that when a write command and a read command for the same vector data unit entry are consecutive, the read data does not overtake the write data and the useless waiting time can be eliminated. An object is to provide an instruction issue control device for a vector processing device.

[0014]

According to the present invention, n (n is an integer of 2 or more) vector data memories each of which stores vector data composed of a plurality of data elements and each has a plurality of entries, and access to the memories. A write / read instruction issue control device in a vector processing device, which includes means for sequentially and repeatedly generating slot timings, which are timings, as first to nth slot numbers, wherein a use entry number and a use slot number of a preceding write instruction are used. Holding means for holding until the end of the writing operation,
Entry match detection means for detecting a match between a used entry number of a subsequent read instruction and a used entry number held by the entry holding means, and the write instruction is issued when a match is detected by the match detection means After a predetermined time determined by the execution time of this instruction, the means for controlling the issuance of the read instruction when a vacant slot other than the used slot held by the holding means arrives, and the match detection means do not match Is detected, a command issuing control device is provided which includes means for immediately controlling the issuance of the read command when an empty slot other than the used slot held in the holding means arrives. ..

[0015]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a schematic block diagram of an embodiment of the present invention. The instruction control unit 10 holds an instruction register 11 for holding a next issued instruction, and a use for holding an entry number of a vector data unit used by this instruction when the instruction held by this instruction register 11 is a vector data unit use instruction. It has an instruction register 12 which decodes the contents of the entry register 17 and the instruction register 11.

The instruction decoder 12 outputs a control signal to the write control circuit 13 when the next issue instruction is a vector data unit write instruction, and to the read control circuit 14 when the next issue instruction is a vector data unit read instruction. To do.

Further, the instruction control unit 10 has a write control circuit 13 for writing to the vector data unit, and this control circuit 13
Receives a write control signal from the instruction decoder 12,
If the write path in-use flag 25 and the slot in-use flag 32 in each access path are checked and it is determined that there is an unused path and slot and the write command can be issued, the issue notification register 15 stores the vector data unit. A control signal indicating a write command is set, and the slot number notification register 16 is set by selecting the lowest slot number of the unused slots. In addition, the entry notification register 18 sets the usage entry number held in the usage entry register 17.

Access vector data unit management unit 2
0-1 and 20-2 are prepared respectively corresponding to the access paths to the vector data unit, and in this example, there are two access paths. It is assumed that unused access paths are selected from the youngest. Hereinafter, all the description of the vector data unit management section corresponds to the path selected when the write command is issued.

The flag 25 is set when a write command is issued, lights up until the end of writing, and indicates that the corresponding write path is in use and that the contents of the entry holding circuit 21 and the slot number holding circuit 22 are valid, respectively. It is a busy flag. The entry holding circuit 21 is set with the entry number used by the write instruction held in the use entry register 17 when the write instruction is issued, and holds it until the end of writing.

Similarly, the slot number holding circuit 22 is set with the slot number selected when the write command is issued, and holds it until the end of writing. The entry comparison circuit 23 compares the contents of the entry holding circuit 21 and the used entry register 17 and outputs a coincidence signal when they are equal.

The signal 24 is obtained by logically ANDing the write path in-use flag 25 and the output of the entry comparison circuit with the entry of the vector data unit used in the preceding write instruction and the entry used in the next issue instruction. This is an entry match signal indicating that the operation is being performed.

The timing management unit 30 is a timing management unit that manages the timing of reading and writing the vector data unit. The counter 31 is a slot counter for generating the timing of slots, and keeps counting 0 to n−1, where n is the number of slots.

The flag 32 is a slot-in-use flag which is set corresponding to the slot number used when the vector unit use instruction is issued and lights up until the end of use.

The read slot control circuit 34 compares the value of the slot counter 31 with the slot number corresponding to the flag that is not lit (not used) in the slot busy flag 32, and if they match, vector data A read slot control signal 33 indicating the unit readable timing is sent to the read control circuit 14.

Chaining management units 40-1, 40-2
Is for managing the chaining timing of writing / reading in the vector data unit, and is prepared corresponding to the write path like the vector data unit management unit 20. Hereinafter, all explanations of the chaining management unit correspond to the path selected when the write command is issued.

The first reset means 43 outputs a reset signal after a fixed time (FUT + PPT-n in this embodiment) determined by the FUT, PPT and the number of slots n after the write command is issued. Is. The first check inhibition flag 41 is set when the write command is issued and reset by the reset signal from the first reset means 43, and inhibits the operation of the second reset means 44 for resetting the second check inhibition flag 42. To do.

The second reset means 44 stores the slot number holding circuit 2 after the first check inhibition flag is reset.
Slot number and slot counter 3 used by the preceding vector data unit write instruction held in 2
The value of 1 is compared with the value of 1, and the second check inhibition flag 42 is reset when a certain relationship (when they are equal in this embodiment) is established.

The second check inhibition flag 42 is set at the same time as the first check inhibition flag 41 when the write instruction is issued, and inhibits the issue control of the vector data unit read instruction reset by the second reset means 44. is there.

The read control circuit 14 is a read control circuit for the vector data unit. When receiving the read control signal from the instruction decoder 12, the read control circuit 14 outputs the entry match signal 24 from the vector data unit management units 20-1 and 20-2 and the timing control. The value of the slot counter 31 and the read slot control signal 33 from the unit 30 are transferred from the chaining management units 40-1 and 40-2 to the second check inhibition flag 42.
When the entry match signals 24 corresponding to the write paths are not lit, the read notification is sent to the issue notification register 15 at the timing when the read slot control signal 33 from the timing management unit 30 is lit. A control signal indicating a vector data read instruction is set, the value of the slot counter 31 at that time is set in the slot number notification register 16, and the value of the used entry register is set in the entry notification register 18. (Issue of read command).

When even one entry match signal 24 is lit, the second check inhibition flag 42 of the chaining management units 40-1 and 40-2 corresponding to the lit entry match signal 24. The read command is not controlled until is reset, but the read command is controlled to be issued at the timing when the read slot control signal 33 first lights up after the second check inhibition flag 42 is reset.

Next, the operation of the present invention will be described using an actual instruction sequence. Now, for the sake of explanation, the vector operation instruction F
The UT is "7", the PPT is "3", the number of slots n is "4", and the number of access paths to the vector data unit is "2".

FIG. 5 is a schematic time chart when the following instruction sequence is executed in the instruction issue control device of the present invention.

VADD VD0 ← VR0 + VR1 VMDA VR2 ← VD0 In the above instruction, VADD adds the vector registers VR0 and VR1 and outputs the operation result to the vector data unit entry 0.
This is an instruction to write to (VD0). VMDA is an instruction to read data from entry 0 (VD0) of the vector data unit and transfer it to the vector register VR2. It is assumed that no instruction using the vector data unit is operating before this instruction sequence operates.

First, when VADD enters the instruction register 11, the instruction decoder 12 detects that it is a vector data unit write instruction and outputs a write control signal to the write control circuit 13. The write control circuit 13 checks the slot busy flag 32 and the write path busy flag 25, and issues an instruction if the slot and write path are free.

At this moment, the vector data unit use instruction is in an issuable state because nothing is operating, the lowest number "0" is selected for the slot and the lowest number "0" is selected for the write path, and the instruction is issued. It At the same time, the write path busy flag 25 of the vector data unit 20-1 corresponding to the write path 0 is set to “1”, the entry holding circuit 21 is set to the entry number “0” of the vector data unit, and the slot number holding circuit 22 is set. Slot number to use "0"
Is set and held until the end of writing.

Also, the flag corresponding to slot 0 of the slot busy flag 32 of the timing management unit 30 is set to "1".
Set and hold until the end of writing. For an unused slot, the slot in-use flag 32 remains “0”, and if the slot number for which the slot in-use flag 32 is “0” and the value of the slot counter 31 match, A read slot control signal 33 is sent from the read slot control circuit 34 to the read control circuit 14 at "1".

The first check inhibition flag 41 and the second check inhibition flag 42 of the chaining management unit 40-1 corresponding to the write path 0 are set to "1" when the VADD instruction is issued, and the first check inhibition is performed. The flag 41 is set by the first reset means 43 after the time determined from the FUT, the PPT, and the number of slots n (in the present description, FUT +
PPT-n, and thus "6" T later).

Further, the second check inhibition flag 42 is set by the second reset means to the first check inhibition flag 4
After the value 1 is reset, it is reset when the value of the slot counter 31 and the value of the slot number holding circuit 22 have a certain relationship (when they are equal in this description).

When the VADD instruction is issued and notified in the vector data unit, the operation result is written in VD0. Therefore, the timing adjustment buffer is waited until the timing of the notified used slot number is reached (see FIG. 2T in the time chart), write continuously to VD0 when there is a timing.

When VMDA enters the instruction register 11 after issuing VADD, the instruction decoder 12 outputs a vector data unit read control signal to the read control circuit 14. The slot busy flag 32 indicates that 1, 2, and 3 are unused, and the read slot control signal 33 indicating that the vector data unit can be read from the timing management unit 30.
Is output at the timing of slot counters 1, 2, and 3, but is used by VMDA and entry VD0 of the vector data unit used in VADD (held as "0" in entry holding circuit 21). Since the entry VD0 of the vector data unit (which exists as "0" in the used entry register) matches, the entry match signal 24 is output from the vector data unit management unit 20-1.

At this time, the read control circuit 14 does not perform control for issuing an instruction until the second check inhibition flag 42 is reset, and after the flag 42 is reset, the read slot control signal 33 first lights up. A VMDA instruction is issued at the timing (in this description, slot "1").
The used slot number selected at this time is the value of the slot counter 31 for which the read slot control signal 33 is lit,
That is, the slot is "1".

When the VMDA instruction is issued as described above, the read operation is started as it is because the vector data unit has the same slot "1" as the notified slot number at which the read operation start timing is notified. ..

When the instruction issuance is controlled as described above, when viewed from the vector data unit, the writing to VD0 and the reading from VD0 are deviated by 1T, that is, the next timing of writing (as the processing timing for the same element, Is the fastest).

Next, in order to explain the case where the entries do not match in the vector data unit, the following instruction sequence is executed.

VADD VD0 ← VR0 + VR1 VMDA VR2 ← VD1 The operation time chart in this case is shown in FIG.

Issuing the VADD instruction and setting each flag are the same as in the above case. When the VMDA instruction is set in the instruction register 11, the instruction decoder 12 sends a read control signal to the read control circuit 14. At this time, the used entry register 17 holds "1" indicating VD1 and does not match the value "0" of the entry holding circuit 21 holding the entry number used by the preceding VADD. Therefore, the entry match signal 24 is not issued. Therefore, the read control circuit 14 issues an instruction at the timing when the read slot control signal 33 first lights up, without waiting for the second check inhibition flag 42 to be reset. The entries in the vector data unit are not identical, so there is no need to wait for the preceding VADD to initiate a write operation to the vector data unit.

The time chart shown in FIG. 6B is a time chart showing the conventional instruction execution.
VMDA that follows is always waiting for the end of instruction execution of the preceding VADD regardless of whether the entries match or not, and issues VMDA to ensure that the read operation in the case of the same entry does not overtake the write data. is doing.
Therefore, in the conventional device, the processing speed was significantly reduced.

[0049]

As described above, according to the present invention, when the read command issuance following the write command to the vector data unit is issued, when the entries match, the write data is not overtaken and read without wasteful waiting time. Since it is performed after waiting for the shortest time necessary for the above, and when the entries do not match, it is performed immediately, there is an effect that the vector processing speed can be remarkably improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a typical configuration example of a vector data unit.

FIG. 3 is a time chart showing an operation example of the vector data unit of FIG.

FIG. 4 is a schematic block diagram of a vector processing device including a vector data unit.

FIG. 5 is a time chart showing an operation of the embodiment of the present invention.

FIG. 6A is a time chart showing another operation of the embodiment of the present invention, and FIG. 6B is a time chart showing an operation of the conventional device.

[Explanation of symbols]

 10 instruction control unit 11 instruction register 12 instruction decoder 13 write control circuit 14 read control circuit 17 use entry register 20-1, 20-2 vector data management unit 21 entry holding circuit 22 slot number holding circuit 23 entry comparison circuit 30 timing management unit 31 slot counter 32 slot in-use flag 34 read slot control circuit 40-1, 40-2 chaining management section 41 first check inhibition flag 42 second check inhibition flag 43 first reset means 44 second reset means

Claims (1)

[Claims] 1. An n, each of which stores vector data composed of a plurality of data elements and has a plurality of entries, respectively.
A write / read instruction in a vector processing device including a plurality (n is an integer of 2 or more) of vector data memory and means for sequentially and repeatedly generating slot timings, which are access timings to the memory, as the first to nth slot numbers. In the issue control device, holding means for holding the used entry number and used slot number of the preceding write instruction until the end of the write operation, the used entry number of the subsequent read instruction and the used entry held by the entry holding means Entry match detection means for detecting a match with a number, and when a match is detected by this match detection means, held by the holding means after a predetermined time determined by the execution time of the write command after the write command is issued. Read the above when an empty slot other than the used slot has arrived. Means for controlling the issue of the read instruction and the match detecting means for detecting a mismatch, and immediately controlling the issue of the read instruction when an empty slot other than the used slot held by the holding means arrives. And a command issuing control device.