JPS56124953A - Instruction fetch system - Google Patents
Instruction fetch systemInfo
- Publication number
- JPS56124953A JPS56124953A JP2655280A JP2655280A JPS56124953A JP S56124953 A JPS56124953 A JP S56124953A JP 2655280 A JP2655280 A JP 2655280A JP 2655280 A JP2655280 A JP 2655280A JP S56124953 A JPS56124953 A JP S56124953A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- latched
- ibr
- overhead
- access
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
Abstract
PURPOSE:To obtain a profitable instruction fetch system which is suitable for a semiconductor memory, by increasing the number of instruction buffer registers, increasing the number of times of fetching a instruction continuously from the main storage, and reducing the overhead. CONSTITUTION:A main storage MS110 of N byte width by a semiconducdor memory element is placed, and a storage control unit SCU12 being a control logic is connected to this MS110. Also, to this SCU120 are connected the instruction unit IU130 on which M pieces of instruction buffer registers IBR150, 151 of N byte width for latching a fetched instruction are provided, and the execution unit EU140 for executing the instruction latched by the IU130. And, the access is repeated by the number of times of M to the same bank of the MS, the instruction group which has been read out is latched to the IBR's 150, 151, the access of the second time and thereafter is executed in the first half of the execution cyclie of the instruction which has been latched to the IBR's 150, 151, and the overhead is reduced.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2655280A JPS56124953A (en) | 1980-03-05 | 1980-03-05 | Instruction fetch system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2655280A JPS56124953A (en) | 1980-03-05 | 1980-03-05 | Instruction fetch system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56124953A true JPS56124953A (en) | 1981-09-30 |
Family
ID=12196678
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2655280A Pending JPS56124953A (en) | 1980-03-05 | 1980-03-05 | Instruction fetch system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56124953A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59180635A (en) * | 1983-03-31 | 1984-10-13 | Fujitsu Ltd | Method for controlling prefetch of instruction |
JPS61285542A (en) * | 1985-06-12 | 1986-12-16 | Mitsubishi Electric Corp | Instruction prefetching method |
-
1980
- 1980-03-05 JP JP2655280A patent/JPS56124953A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59180635A (en) * | 1983-03-31 | 1984-10-13 | Fujitsu Ltd | Method for controlling prefetch of instruction |
JPS61285542A (en) * | 1985-06-12 | 1986-12-16 | Mitsubishi Electric Corp | Instruction prefetching method |
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