JPS5734253A - Brunch instruction controlling circuit - Google Patents

Brunch instruction controlling circuit

Info

Publication number
JPS5734253A
JPS5734253A JP10881780A JP10881780A JPS5734253A JP S5734253 A JPS5734253 A JP S5734253A JP 10881780 A JP10881780 A JP 10881780A JP 10881780 A JP10881780 A JP 10881780A JP S5734253 A JPS5734253 A JP S5734253A
Authority
JP
Japan
Prior art keywords
general register
busses
read
controlling circuit
brunch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10881780A
Other languages
Japanese (ja)
Inventor
Kazuyuki Shimizu
Katsumi Onishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10881780A priority Critical patent/JPS5734253A/en
Publication of JPS5734253A publication Critical patent/JPS5734253A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G06F9/381—Loop buffering

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)

Abstract

PURPOSE:To determine success or snsuccess of reading without increasing read busses by detecting that a content of a general register indicated at a general bus assigning part in read busses is one in a case where an empty of at least one system exists in the read busses of the general register. CONSTITUTION:Read address registers A1, B1, C1, AB for general register for each timing in counting branch instruction are provided in a read address selecting circuit 12, and registers A1, B1, AX, C2 are given in read address selecting circuit 13. Further, an output of reading busses 14, 15 in a general register 11 detects with a branch instruction controlling circuit 16 whether a content of the general register indicated with a general register assigning part is one or not, thereby allowing success or unsuccess in the branch to be determined.
JP10881780A 1980-08-09 1980-08-09 Brunch instruction controlling circuit Pending JPS5734253A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10881780A JPS5734253A (en) 1980-08-09 1980-08-09 Brunch instruction controlling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10881780A JPS5734253A (en) 1980-08-09 1980-08-09 Brunch instruction controlling circuit

Publications (1)

Publication Number Publication Date
JPS5734253A true JPS5734253A (en) 1982-02-24

Family

ID=14494257

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10881780A Pending JPS5734253A (en) 1980-08-09 1980-08-09 Brunch instruction controlling circuit

Country Status (1)

Country Link
JP (1) JPS5734253A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61253541A (en) * 1985-05-07 1986-11-11 Hitachi Ltd Instruction processor
JPS6341932A (en) * 1985-08-22 1988-02-23 Nec Corp Branching instruction processing device
US5213329A (en) * 1990-09-25 1993-05-25 The Yokohama Rubber Co., Ltd. Golf club head

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61253541A (en) * 1985-05-07 1986-11-11 Hitachi Ltd Instruction processor
JPS6341932A (en) * 1985-08-22 1988-02-23 Nec Corp Branching instruction processing device
US5213329A (en) * 1990-09-25 1993-05-25 The Yokohama Rubber Co., Ltd. Golf club head

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