JPS6425261A - Microprocessor system - Google Patents

Microprocessor system

Info

Publication number
JPS6425261A
JPS6425261A JP62181367A JP18136787A JPS6425261A JP S6425261 A JPS6425261 A JP S6425261A JP 62181367 A JP62181367 A JP 62181367A JP 18136787 A JP18136787 A JP 18136787A JP S6425261 A JPS6425261 A JP S6425261A
Authority
JP
Japan
Prior art keywords
memory
data
bus
exceptional
stack cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62181367A
Other languages
Japanese (ja)
Inventor
Toshiyuki Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62181367A priority Critical patent/JPS6425261A/en
Publication of JPS6425261A publication Critical patent/JPS6425261A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To improve process efficiency by once saving the data of a register to a memory for a stack cache through a bus when an exceptional case occurs, thereafter saving the saved data to an external memory with utilizing the empty cycle of the bus. CONSTITUTION:A control circuit 12 saves data in respective registers Reg1-Reg(n) simultaneously to the memory for a stack cache 11 through buses BS1-BS(n) in case of receiving an interrupt notice or an exceptional process notice. Next, the data in the memory for the stack cache 11 are successively saved to an external memory 2 by utilizing the empty cycle of the bus BS while a microprocessor 1 executes the interruption processing and the exceptional processing.
JP62181367A 1987-07-21 1987-07-21 Microprocessor system Pending JPS6425261A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62181367A JPS6425261A (en) 1987-07-21 1987-07-21 Microprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62181367A JPS6425261A (en) 1987-07-21 1987-07-21 Microprocessor system

Publications (1)

Publication Number Publication Date
JPS6425261A true JPS6425261A (en) 1989-01-27

Family

ID=16099486

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62181367A Pending JPS6425261A (en) 1987-07-21 1987-07-21 Microprocessor system

Country Status (1)

Country Link
JP (1) JPS6425261A (en)

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