JPS57108952A - Busy control system - Google Patents

Busy control system

Info

Publication number
JPS57108952A
JPS57108952A JP18611180A JP18611180A JPS57108952A JP S57108952 A JPS57108952 A JP S57108952A JP 18611180 A JP18611180 A JP 18611180A JP 18611180 A JP18611180 A JP 18611180A JP S57108952 A JPS57108952 A JP S57108952A
Authority
JP
Japan
Prior art keywords
bank
access
port
bank number
discrimination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18611180A
Other languages
Japanese (ja)
Inventor
Mikio Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18611180A priority Critical patent/JPS57108952A/en
Publication of JPS57108952A publication Critical patent/JPS57108952A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To speed up continuous access by enabling the access on some condition even when a main storage device is in a busy state as a result of partial storage in a memory bank in the main storage device. CONSTITUTION:A discrimination partIfor a port A has shift registers 1-3, a comparing circuit 5, and an NOR circuit 6. The register 1 has a bank number 1-0 and a valid flag 1-1; the number of a bank at an access destination is entered in the bank number 1-0, and access to the bank with the bank number is entered into the valid flag 1-1. The comparing circuit 4 compares the bank number of the register 3 with the bank number of the access destination transferred to a port B. When an access request is sent from the port A while an- other access request is sent by a vector unit to a main storage controller MCU, a discrimination part II for the port B generates a control signal for permitting the access request on the same conditions with the discrimination partIfor the port A.
JP18611180A 1980-12-25 1980-12-25 Busy control system Pending JPS57108952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18611180A JPS57108952A (en) 1980-12-25 1980-12-25 Busy control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18611180A JPS57108952A (en) 1980-12-25 1980-12-25 Busy control system

Publications (1)

Publication Number Publication Date
JPS57108952A true JPS57108952A (en) 1982-07-07

Family

ID=16182545

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18611180A Pending JPS57108952A (en) 1980-12-25 1980-12-25 Busy control system

Country Status (1)

Country Link
JP (1) JPS57108952A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4538056A (en) * 1982-08-27 1985-08-27 Figgie International, Inc. Card reader for time and attendance
US4544832A (en) * 1982-08-27 1985-10-01 Figgie International, Inc. Card reader with buffer for degraded mode
JPS61239341A (en) * 1985-04-16 1986-10-24 Fujitsu Ltd Memory busy checking system
JPS6240565A (en) * 1985-08-15 1987-02-21 Hitachi Ltd Memory control system
US4816658A (en) * 1983-01-10 1989-03-28 Casi-Rusco, Inc. Card reader for security system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4538056A (en) * 1982-08-27 1985-08-27 Figgie International, Inc. Card reader for time and attendance
US4544832A (en) * 1982-08-27 1985-10-01 Figgie International, Inc. Card reader with buffer for degraded mode
US4816658A (en) * 1983-01-10 1989-03-28 Casi-Rusco, Inc. Card reader for security system
JPS61239341A (en) * 1985-04-16 1986-10-24 Fujitsu Ltd Memory busy checking system
JPS6240565A (en) * 1985-08-15 1987-02-21 Hitachi Ltd Memory control system

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