JPS5724085A - Information process system - Google Patents

Information process system

Info

Publication number
JPS5724085A
JPS5724085A JP9779880A JP9779880A JPS5724085A JP S5724085 A JPS5724085 A JP S5724085A JP 9779880 A JP9779880 A JP 9779880A JP 9779880 A JP9779880 A JP 9779880A JP S5724085 A JPS5724085 A JP S5724085A
Authority
JP
Japan
Prior art keywords
address
cpu0
buffer
bus
invalidating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9779880A
Other languages
Japanese (ja)
Inventor
Hiroshi Tamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9779880A priority Critical patent/JPS5724085A/en
Publication of JPS5724085A publication Critical patent/JPS5724085A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Abstract

PURPOSE:To invalidate process of a buffer memory in a simple and effective way, by controlling the address effective display bit in an address buffer in accordance with the address on a signal bus. CONSTITUTION:A channel processor CHP, a CPU0, a CPU1 and a vector processor VPU have a common access to a main memory MEM via a control device MCU. The MCU checks the busy state of the MEM to select one of the accesses during a conflict of addesses and at the same time transmits a buffer invalidating address and a invalidating indication signal to the CPU0 and CPU1. When the CPU0 is loaded, the address of the CPU0 is sent to a buffer invalidating address sending part of the CPU0 side via bus l1 or l2. Then a comparator ADC examines whether or not an address equal to the address on the bus l1 or l2 exists in the address group in which the address effective display bit in an address buffer is on, and then turns off the effective display bit of the address in case an address equal to that on the bus l1 or l2 exists.
JP9779880A 1980-07-16 1980-07-16 Information process system Pending JPS5724085A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9779880A JPS5724085A (en) 1980-07-16 1980-07-16 Information process system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9779880A JPS5724085A (en) 1980-07-16 1980-07-16 Information process system

Publications (1)

Publication Number Publication Date
JPS5724085A true JPS5724085A (en) 1982-02-08

Family

ID=14201808

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9779880A Pending JPS5724085A (en) 1980-07-16 1980-07-16 Information process system

Country Status (1)

Country Link
JP (1) JPS5724085A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6345654A (en) * 1986-08-13 1988-02-26 Nec Corp Invalidation processing system for information processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6345654A (en) * 1986-08-13 1988-02-26 Nec Corp Invalidation processing system for information processor

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