JPS5487437A - Memory dump processing system by way of channel - Google Patents

Memory dump processing system by way of channel

Info

Publication number
JPS5487437A
JPS5487437A JP15595577A JP15595577A JPS5487437A JP S5487437 A JPS5487437 A JP S5487437A JP 15595577 A JP15595577 A JP 15595577A JP 15595577 A JP15595577 A JP 15595577A JP S5487437 A JPS5487437 A JP S5487437A
Authority
JP
Japan
Prior art keywords
data processor
memory
channel connection
connection unit
dump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15595577A
Other languages
Japanese (ja)
Other versions
JPS5821738B2 (en
Inventor
Makoto Awata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP52155955A priority Critical patent/JPS5821738B2/en
Publication of JPS5487437A publication Critical patent/JPS5487437A/en
Publication of JPS5821738B2 publication Critical patent/JPS5821738B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • Computer And Data Communications (AREA)

Abstract

PURPOSE: To make it possible to attain a memory dump in a short time by amking it possible to dump the contents of a memory unit, by providing a simple firmware function to a channel connection unit and giving a dump command.
CONSTITUTION: Channels 2-0 and 2-1 and channel connection unit 3 are provided which connect two data processors 1-0 and 1-1 and data processors 1-0 and 1-1, and channel connection unit 3 is provided with firmware function part 9 consisting of microprocessor 10 and control memory 11. Further, data processor 1-1 is equipped with processor part 8 and memory unit 6, and data processor 1-0 is with processing function part 7 and memory unit 5; data processor 1-0 serves for the host data processor. Then, a dump command is transmitted to channel connection unit 3 from data processor 1-0, access to memory unit 6 of data processor 1-1 is made by function part 9 of channel connection unit 3, and memory contents within the range indicated by the command from the fixed address position are read out in seqeuence and stored in memory unit 5.
COPYRIGHT: (C)1979,JPO&Japio
JP52155955A 1977-12-23 1977-12-23 Memory dump processing method via channel Expired JPS5821738B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52155955A JPS5821738B2 (en) 1977-12-23 1977-12-23 Memory dump processing method via channel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52155955A JPS5821738B2 (en) 1977-12-23 1977-12-23 Memory dump processing method via channel

Publications (2)

Publication Number Publication Date
JPS5487437A true JPS5487437A (en) 1979-07-11
JPS5821738B2 JPS5821738B2 (en) 1983-05-02

Family

ID=15617174

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52155955A Expired JPS5821738B2 (en) 1977-12-23 1977-12-23 Memory dump processing method via channel

Country Status (1)

Country Link
JP (1) JPS5821738B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7076286B2 (en) 2018-05-25 2022-05-27 理想科学工業株式会社 Printing systems, wearable terminals and programs

Also Published As

Publication number Publication date
JPS5821738B2 (en) 1983-05-02

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