JPS55119739A - Binary-decimal conversion system - Google Patents

Binary-decimal conversion system

Info

Publication number
JPS55119739A
JPS55119739A JP2745979A JP2745979A JPS55119739A JP S55119739 A JPS55119739 A JP S55119739A JP 2745979 A JP2745979 A JP 2745979A JP 2745979 A JP2745979 A JP 2745979A JP S55119739 A JPS55119739 A JP S55119739A
Authority
JP
Japan
Prior art keywords
decimal
binary
adder
digit
correction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2745979A
Other languages
Japanese (ja)
Inventor
Yukichi Ikuta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2745979A priority Critical patent/JPS55119739A/en
Publication of JPS55119739A publication Critical patent/JPS55119739A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To decrease the hardware without increasing the conversion processing- time, without correction of the decimal digit when the most significant bit of the shifter is "1", and by decimal correction by reducing "6" from the decimal digit in other cases.
CONSTITUTION: In the system converting the binary number B into binary decimal number according to equation I, the two input decimal adder 13 has binary coded decimal number to one input A0 and +6 is inputted to another input A1 in response to each decimal number. Further, the register 15 stores the binary coded decimal number output of the adder 13, the register 16 stores the binary number to perform binary-decimal conversion, the shifters 17, 18 shift left by one bit the content of the registers 15, 16, and it is inputted to A0 of the adder 13. When the most significant bit of the decimal digit of the shifter 17 is "1" or in case of binary addition, if carry is produced from the most significant bit of the decimal digit, the adder 13 does not perform the correction 14 of the decimal digit and if any of them is not established, "6" is subtracted from the decimal digit for decimal correction 14. Thus, without increasing the conversion processing time, the amount of hardware can be reduced.
COPYRIGHT: (C)1980,JPO&Japio
JP2745979A 1979-03-09 1979-03-09 Binary-decimal conversion system Pending JPS55119739A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2745979A JPS55119739A (en) 1979-03-09 1979-03-09 Binary-decimal conversion system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2745979A JPS55119739A (en) 1979-03-09 1979-03-09 Binary-decimal conversion system

Publications (1)

Publication Number Publication Date
JPS55119739A true JPS55119739A (en) 1980-09-13

Family

ID=12221694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2745979A Pending JPS55119739A (en) 1979-03-09 1979-03-09 Binary-decimal conversion system

Country Status (1)

Country Link
JP (1) JPS55119739A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59168543A (en) * 1983-03-16 1984-09-22 Jido Keisoku Gijutsu Kenkiyuukumiai Binary-decimal converting circuit
US4493708A (en) * 1981-12-10 1985-01-15 Terumo Corporation Intravascular catheter assembly

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4493708A (en) * 1981-12-10 1985-01-15 Terumo Corporation Intravascular catheter assembly
JPS59168543A (en) * 1983-03-16 1984-09-22 Jido Keisoku Gijutsu Kenkiyuukumiai Binary-decimal converting circuit

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