JPS575430A - Binary coded decimal converter - Google Patents
Binary coded decimal converterInfo
- Publication number
- JPS575430A JPS575430A JP7909580A JP7909580A JPS575430A JP S575430 A JPS575430 A JP S575430A JP 7909580 A JP7909580 A JP 7909580A JP 7909580 A JP7909580 A JP 7909580A JP S575430 A JPS575430 A JP S575430A
- Authority
- JP
- Japan
- Prior art keywords
- output
- block
- signal
- coded decimal
- binary coded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/02—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word
- H03M7/06—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word the radix thereof being a positive integer different from two
- H03M7/08—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word the radix thereof being a positive integer different from two the radix being ten, i.e. pure decimal code
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
PURPOSE:To enable high-speed processing, by converting a pure binary number into a binary coded decimal with a simplified processor. CONSTITUTION:A pure binary number to be converted is set to a P of a shift register 10 and the number of bits in a pure binary number to be set is set to a monitor circuit 16. The shift register 10 is shifted left by one bit every output of a controller 18 having a 3-bit counter. In this case, ''0'' is inserted to the least significant bit. Next, one block Q0 out of a column Q is selected in a multiplexer 11, based on a 3-bit counter of the controller 18, the content of the block Q0 is compared with 5(=0101) with a comparator 13, and if the result is more than the value, a YES signal is applied to a gate 14. On the other hand, 3 is added to the block Q0 with an adder 12, and the signal output and one of an output not added with 3 are applied to the gate circuit 14 and the result is selected with the YES signal being the output signal of the comparator 13.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7909580A JPS575430A (en) | 1980-06-13 | 1980-06-13 | Binary coded decimal converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7909580A JPS575430A (en) | 1980-06-13 | 1980-06-13 | Binary coded decimal converter |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS575430A true JPS575430A (en) | 1982-01-12 |
Family
ID=13680315
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7909580A Pending JPS575430A (en) | 1980-06-13 | 1980-06-13 | Binary coded decimal converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS575430A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6285030U (en) * | 1985-11-18 | 1987-05-30 |
-
1980
- 1980-06-13 JP JP7909580A patent/JPS575430A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6285030U (en) * | 1985-11-18 | 1987-05-30 |
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