JPS5771045A - Digital mulitplier - Google Patents

Digital mulitplier

Info

Publication number
JPS5771045A
JPS5771045A JP14680780A JP14680780A JPS5771045A JP S5771045 A JPS5771045 A JP S5771045A JP 14680780 A JP14680780 A JP 14680780A JP 14680780 A JP14680780 A JP 14680780A JP S5771045 A JPS5771045 A JP S5771045A
Authority
JP
Japan
Prior art keywords
data
bit
multiplicand
order prescribed
prescribed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14680780A
Other languages
Japanese (ja)
Inventor
Masanori Ishibashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP14680780A priority Critical patent/JPS5771045A/en
Publication of JPS5771045A publication Critical patent/JPS5771045A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/527—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel
    • G06F7/5272—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel with row wise addition of partial products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To reduce arithmetic errors greatly while simplifying circuit constitution, by correcting the high-order prescribed-bit data according to the contents of data one bit lower than the high-order prescribed-bit data of multiplicand data. CONSTITUTION:The contents of data one bit lower than the high-order prescribed- bit data of multiplicand data A are detected, and according to the detection result, the high-order prescribed bit of the multiplicand data A is corrected. On the basis of the corrected prescribed bit data, a full-adder circuit 4 adds the multiplicand data A and multiplier data B toghether and the addition output is latched by a latch circuit 18 to be sent out as arithmetic result data O7-O0 showing the high-order prescribed eight bits of the arithmetic result data A.B.
JP14680780A 1980-10-22 1980-10-22 Digital mulitplier Pending JPS5771045A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14680780A JPS5771045A (en) 1980-10-22 1980-10-22 Digital mulitplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14680780A JPS5771045A (en) 1980-10-22 1980-10-22 Digital mulitplier

Publications (1)

Publication Number Publication Date
JPS5771045A true JPS5771045A (en) 1982-05-01

Family

ID=15415966

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14680780A Pending JPS5771045A (en) 1980-10-22 1980-10-22 Digital mulitplier

Country Status (1)

Country Link
JP (1) JPS5771045A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63198125A (en) * 1987-02-13 1988-08-16 Nec Corp Multiplication circuit
JPH01193933A (en) * 1988-01-28 1989-08-03 Nec Corp Digital multiplier

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5386539A (en) * 1977-01-10 1978-07-31 Hitachi Ltd Arithmetic unit
JPS55121544A (en) * 1979-03-14 1980-09-18 Hitachi Ltd Multiplication rounding circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5386539A (en) * 1977-01-10 1978-07-31 Hitachi Ltd Arithmetic unit
JPS55121544A (en) * 1979-03-14 1980-09-18 Hitachi Ltd Multiplication rounding circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63198125A (en) * 1987-02-13 1988-08-16 Nec Corp Multiplication circuit
JPH01193933A (en) * 1988-01-28 1989-08-03 Nec Corp Digital multiplier

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